From patchwork Thu Feb 12 06:37:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 439094 X-Patchwork-Delegate: iwamatsu@nigauri.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 479DE14017A for ; Thu, 12 Feb 2015 17:37:56 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4A300A744B; Thu, 12 Feb 2015 07:37:51 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GIXjW0OOkC4u; Thu, 12 Feb 2015 07:37:51 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A16B0A7450; Thu, 12 Feb 2015 07:37:46 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C30DF4B576 for ; Thu, 12 Feb 2015 07:37:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z6bhb_SjZCAI for ; Thu, 12 Feb 2015 07:37:42 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f170.google.com (mail-pd0-f170.google.com [209.85.192.170]) by theia.denx.de (Postfix) with ESMTPS id 47D3D4A03B for ; Thu, 12 Feb 2015 07:37:40 +0100 (CET) Received: by pdno5 with SMTP id o5so9869553pdn.8 for ; Wed, 11 Feb 2015 22:37:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=UNDf8neTI++QcE6O/HKKdEBaCCuaBfVvANXHiRmxb1c=; b=Uc03e3MMfMZPzGivwURrivsvcKx2/xHzzDyY1vxie/b1+e+WuizJhk03JUH2c2HC+R z+7FAMmSR6+70CgxdedJLoz6FWmCM2wjyg8XAfs4X2DavSENY3qN+g7u1F8C7LdgZlZM iCNZGBr5Z0Juch20ZHp2zPgOwMclfAzVV8vSGOiKUNtUK0On4eeLW7YHVV1Cxf/4ISFj dvVkHEqZrkEt9MHxkYMVh9cd1Hh03ER/QKtizuVsqWC/fdq2sjPVqtiPkizQfdONsOfm t8sGSICw3deMNEcsAU7yAQZhGL7UFA5YeNhpednZThjFpqxRkgJDKh//cQNK5AYNUnYw /E2w== X-Gm-Message-State: ALoCoQkkhfX/1KMqapkCLftF/p+5k0ummzkb/JCW+XbgUA0VJ1j0I+7IGYIZoQOlZYExRoefOao7 X-Received: by 10.68.125.197 with SMTP id ms5mr4201395pbb.12.1423723058750; Wed, 11 Feb 2015 22:37:38 -0800 (PST) Received: from xps-iwamatsu.renesas.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id o4sm2715921pdn.3.2015.02.11.22.37.36 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Feb 2015 22:37:37 -0800 (PST) From: Nobuhiro Iwamatsu To: u-boot@lists.denx.de, Nobuhiro Iwamatsu Date: Thu, 12 Feb 2015 15:37:19 +0900 Message-Id: <1423723041-31887-2-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1423723041-31887-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> References: <1423723041-31887-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> Cc: Nobuhiro Iwamatsu Subject: [U-Boot] [PATCH 2/4] arm: rmobile: koelsch: Add support SDHI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Koelsch board has three SDHI port. This adds GPIO configuration and initialization function of SDHI, and enables MMC command. Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/koelsch/koelsch.c | 72 +++++++++++++++++++++++++++++++++++++++++ configs/koelsch_defconfig | 1 + include/configs/koelsch.h | 7 +++- 3 files changed, 79 insertions(+), 1 deletion(-) diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index f627433..51e70e2 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,14 @@ void s_init(void) #define SCIF0_MSTP721 (1 << 21) #define ETHER_MSTP813 (1 << 13) +#define SDHI0_MSTP314 (1 << 14) +#define SDHI1_MSTP312 (1 << 12) +#define SDHI2_MSTP311 (1 << 11) + +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + int board_early_init_f(void) { mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); @@ -60,6 +69,17 @@ int board_early_init_f(void) /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + /* SDHI */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, + SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD1 and SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD1CKCR); + writel(SD_97500KHZ, SD2CKCR); + return 0; } @@ -128,6 +148,58 @@ int board_eth_init(bd_t *bis) #endif } +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; + +#ifdef CONFIG_SH_SDHI + gpio_request(GPIO_FN_SD0_DATA0, NULL); + gpio_request(GPIO_FN_SD0_DATA1, NULL); + gpio_request(GPIO_FN_SD0_DATA2, NULL); + gpio_request(GPIO_FN_SD0_DATA3, NULL); + gpio_request(GPIO_FN_SD0_CLK, NULL); + gpio_request(GPIO_FN_SD0_CMD, NULL); + gpio_request(GPIO_FN_SD0_CD, NULL); + gpio_request(GPIO_FN_SD2_DATA0, NULL); + gpio_request(GPIO_FN_SD2_DATA1, NULL); + gpio_request(GPIO_FN_SD2_DATA2, NULL); + gpio_request(GPIO_FN_SD2_DATA3, NULL); + gpio_request(GPIO_FN_SD2_CLK, NULL); + gpio_request(GPIO_FN_SD2_CMD, NULL); + gpio_request(GPIO_FN_SD2_CD, NULL); + + /* SDHI 0 */ + gpio_request(GPIO_GP_7_17, NULL); + gpio_request(GPIO_GP_2_12, NULL); + gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, + SH_SDHI_QUIRK_16BIT_BUF); + if (ret) + return ret; + + /* SDHI 1 */ + gpio_request(GPIO_GP_7_18, NULL); + gpio_request(GPIO_GP_2_13, NULL); + gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); + if (ret) + return ret; + + /* SDHI 2 */ + gpio_request(GPIO_GP_7_19, NULL); + gpio_request(GPIO_GP_2_26, NULL); + gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ + gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); +#endif + return ret; +} + int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index fd7a558..b1e3529 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -3,3 +3,4 @@ CONFIG_RMOBILE=y CONFIG_TARGET_KOELSCH=y CONFIG_DM=y CONFIG_DM_SERIAL=y +CONFIG_SH_SDHI=y diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h index f7c7b2a..1dffab1 100644 --- a/include/configs/koelsch.h +++ b/include/configs/koelsch.h @@ -89,7 +89,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_USB_STORAGE - /* Module stop status bits */ /* INTC-RT */ #define CONFIG_SMSTP0_ENA 0x00400000 @@ -100,4 +99,10 @@ /* SCIF0 */ #define CONFIG_SMSTP7_ENA 0x00200000 +/* SD */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 97500000 + #endif /* __KOELSCH_H */