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[U-Boot,v2,03/11] Exynos542x: Add workaround for ARM errata 798870

Message ID 1422951540-11962-4-git-send-email-akshay.s@samsung.com
State Changes Requested
Delegated to: Minkyu Kang
Headers show

Commit Message

Akshay Saraswat Feb. 3, 2015, 8:18 a.m. UTC 
This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Kimoon Kim <kimoon.kim@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
---
Changes since v1:
	- Added Reviewed-by & Tested-by.
	- Added space before */ on line # 40.

 arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
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Patch

diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
index d599bd3..3ad5b78 100644
--- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
+++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c
@@ -46,6 +46,28 @@  enum {
 
 #ifdef CONFIG_EXYNOS5420
 /*
+ * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
+ * stalled for 1024 cycles to verify that its hazard condition still exists.
+ */
+void set_l2cache(void)
+{
+	uint32_t val;
+
+	/* Read MIDR for Primary Part Number */
+	mrc_midr(val);
+	val = (val >> 4);
+	val &= 0xf;
+
+	/* L2ACTLR[7]: Enable hazard detect timeout for A15 */
+	if (val == 0xf) {
+		mrc_l2_aux_ctlr(val);
+		val |= (1 << 7);
+		mcr_l2_aux_ctlr(val);
+		mrc_l2_ctlr(val);
+	}
+}
+
+/*
  * Pointer to this function is stored in iRam which is used
  * for jump and power down of a specific core.
  */