From patchwork Thu Jan 29 13:56:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 434559 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 698261402B0 for ; Fri, 30 Jan 2015 00:56:37 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4D5134B6F2; Thu, 29 Jan 2015 14:56:34 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id f7drNLVtsc25; Thu, 29 Jan 2015 14:56:34 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C1B994B6CD; Thu, 29 Jan 2015 14:56:33 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6606F4B6CD for ; Thu, 29 Jan 2015 14:56:29 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AzUakWXEuBvo for ; Thu, 29 Jan 2015 14:56:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f174.google.com (mail-wi0-f174.google.com [209.85.212.174]) by theia.denx.de (Postfix) with ESMTPS id 1DA644B6C7 for ; Thu, 29 Jan 2015 14:56:25 +0100 (CET) Received: by mail-wi0-f174.google.com with SMTP id n3so26613662wiv.1 for ; Thu, 29 Jan 2015 05:56:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zG52KjTFraxeFa/ZnTu4upQWV3XTPSITLtxZsrZ7udc=; b=iEguLTwai+DmQQxr7IXWE84O0nps2YnwntHVb0Oe+kwTUPf28rQuji39sYx3XSH8CJ zsV8TMXDraYzPdgQwuOYhEPoIQraNZSnokgpCA+ppKUj8C8YmekMjeZOtkzH1N/52dDG DTq7cw79VO/OfsJEe/RcNfSe0OrgqhOnSY5X2tddvWmt61Oc4HGDtEHvKamk75idSvWi vUE9QNpo/CxY60t9wPZAhwGW/4w5njOThgzWitWE16qL9gryWcXOdb91sx4/6mBSzRC+ 83DA+t8BbkiRowSRXcnMlVtSQZtsSAUrBRf2YG7a3Egkfgwqt8PoxewkVvNqZmoxIaz2 zoJg== X-Received: by 10.180.104.132 with SMTP id ge4mr148169wib.61.1422539785034; Thu, 29 Jan 2015 05:56:25 -0800 (PST) Received: from PC002447.sl.sys.sphairon.com (p4FCC8D1D.dip0.t-ipconnect.de. [79.204.141.29]) by mx.google.com with ESMTPSA id ev7sm10573680wjb.47.2015.01.29.05.56.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Jan 2015 05:56:24 -0800 (PST) From: Daniel Schwierzeck To: u-boot@lists.denx.de Date: Thu, 29 Jan 2015 14:56:20 +0100 Message-Id: <1422539780-11478-1-git-send-email-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1422539029-10994-1-git-send-email-daniel.schwierzeck@gmail.com> References: <1422539029-10994-1-git-send-email-daniel.schwierzeck@gmail.com> Subject: [U-Boot] [PATCH v2] MIPS: unify CPU code in arch/mips/cpu/ X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/. The CPU specific config.mk files need to remain until CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol. Signed-off-by: Paul Burton Signed-off-by: Daniel Schwierzeck --- Changes for v2: - resend with git rename detection enabled --- arch/mips/Makefile | 6 +- arch/mips/cpu/Makefile | 9 + arch/mips/cpu/{mips64 => }/cpu.c | 3 +- arch/mips/cpu/{mips32 => }/interrupts.c | 0 arch/mips/cpu/mips32/Makefile | 9 - arch/mips/cpu/mips32/cpu.c | 34 ---- arch/mips/cpu/mips64/Makefile | 9 - arch/mips/cpu/mips64/interrupts.c | 22 --- arch/mips/cpu/mips64/start.S | 291 -------------------------------- arch/mips/cpu/mips64/time.c | 19 --- arch/mips/cpu/{mips32 => }/start.S | 0 arch/mips/cpu/{mips32 => }/time.c | 0 12 files changed, 13 insertions(+), 389 deletions(-) create mode 100644 arch/mips/cpu/Makefile rename arch/mips/cpu/{mips64 => }/cpu.c (91%) rename arch/mips/cpu/{mips32 => }/interrupts.c (100%) delete mode 100644 arch/mips/cpu/mips32/Makefile delete mode 100644 arch/mips/cpu/mips32/cpu.c delete mode 100644 arch/mips/cpu/mips64/Makefile delete mode 100644 arch/mips/cpu/mips64/interrupts.c delete mode 100644 arch/mips/cpu/mips64/start.S delete mode 100644 arch/mips/cpu/mips64/time.c rename arch/mips/cpu/{mips32 => }/start.S (100%) rename arch/mips/cpu/{mips32 => }/time.c (100%) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ff01bfe..43f0f5c 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -2,11 +2,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -head-$(CONFIG_CPU_MIPS32) := arch/mips/cpu/mips32/start.o -head-$(CONFIG_CPU_MIPS64) := arch/mips/cpu/mips64/start.o +head-y := arch/mips/cpu/start.o -libs-$(CONFIG_CPU_MIPS32) += arch/mips/cpu/mips32/ -libs-$(CONFIG_CPU_MIPS64) += arch/mips/cpu/mips64/ +libs-y += arch/mips/cpu/ libs-y += arch/mips/lib/ libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/ diff --git a/arch/mips/cpu/Makefile b/arch/mips/cpu/Makefile new file mode 100644 index 0000000..fc6b455 --- /dev/null +++ b/arch/mips/cpu/Makefile @@ -0,0 +1,9 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +extra-y = start.o + +obj-y += time.o +obj-y += interrupts.o +obj-y += cpu.o diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/cpu.c similarity index 91% rename from arch/mips/cpu/mips64/cpu.c rename to arch/mips/cpu/cpu.c index 1d32705..8d3b2f5 100644 --- a/arch/mips/cpu/mips64/cpu.c +++ b/arch/mips/cpu/cpu.c @@ -8,10 +8,11 @@ #include #include #include +#include #include #include -void __attribute__((weak)) _machine_restart(void) +void __weak _machine_restart(void) { fprintf(stderr, "*** reset failed ***\n"); diff --git a/arch/mips/cpu/mips32/interrupts.c b/arch/mips/cpu/interrupts.c similarity index 100% rename from arch/mips/cpu/mips32/interrupts.c rename to arch/mips/cpu/interrupts.c diff --git a/arch/mips/cpu/mips32/Makefile b/arch/mips/cpu/mips32/Makefile deleted file mode 100644 index cb4db9c..0000000 --- a/arch/mips/cpu/mips32/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cpu.o interrupts.o time.o diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c deleted file mode 100644 index 07deca8..0000000 --- a/arch/mips/cpu/mips32/cpu.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -void __attribute__((weak)) _machine_restart(void) -{ -} - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - _machine_restart(); - - fprintf(stderr, "*** reset failed ***\n"); - return 0; -} - -void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) -{ - write_c0_entrylo0(low0); - write_c0_pagemask(pagemask); - write_c0_entrylo1(low1); - write_c0_entryhi(hi); - write_c0_index(index); - tlb_write_indexed(); -} diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile deleted file mode 100644 index cb4db9c..0000000 --- a/arch/mips/cpu/mips64/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o -obj-y = cpu.o interrupts.o time.o diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c deleted file mode 100644 index 275fcf5..0000000 --- a/arch/mips/cpu/mips64/interrupts.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -int interrupt_init(void) -{ - return 0; -} - -void enable_interrupts(void) -{ -} - -int disable_interrupts(void) -{ - return 0; -} diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S deleted file mode 100644 index 471bc1e..0000000 --- a/arch/mips/cpu/mips64/start.S +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Startup Code for MIPS64 CPU-core - * - * Copyright (c) 2003 Wolfgang Denk - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifndef CONFIG_SYS_MIPS_CACHE_MODE -#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT -#endif - -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_SP_OFFSET) -#endif - -#ifdef CONFIG_SYS_LITTLE_ENDIAN -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) -#else -#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ - ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) -#endif - - /* - * For the moment disable interrupts, mark the kernel mode and - * set ST0_KX so that the CPU does not spit fire when using - * 64-bit addresses. - */ - .macro setup_c0_status set clr - .set push - mfc0 t0, CP0_STATUS - or t0, ST0_CU0 | \set | 0x1f | \clr - xor t0, 0x1f | \clr - mtc0 t0, CP0_STATUS - .set noreorder - sll zero, 3 # ehb - .set pop - .endm - - .set noreorder - - .globl _start - .text -_start: - /* U-boot entry point */ - b reset - nop - - .org 0x200 - /* TLB refill, 32 bit task */ -1: b 1b - nop - - .org 0x280 - /* XTLB refill, 64 bit task */ -1: b 1b - nop - - .org 0x300 - /* Cache error exception */ -1: b 1b - nop - - .org 0x380 - /* General exception */ -1: b 1b - nop - - .org 0x400 - /* Catch interrupt exceptions */ -1: b 1b - nop - - .org 0x480 - /* EJTAG debug exception */ -1: b 1b - nop - - .align 4 -reset: - - /* Clear watch registers */ - dmtc0 zero, CP0_WATCHLO - dmtc0 zero, CP0_WATCHHI - - /* WP(Watch Pending), SW0/1 should be cleared */ - mtc0 zero, CP0_CAUSE - - setup_c0_status ST0_KX 0 - - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* CONFIG0 register */ - dli t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG -#endif - - /* - * Initialize $gp, force 8 byte alignment of bal instruction to forbid - * the compiler to put nop's between bal and _gp. This is required to - * keep _gp and ra aligned to 8 byte. - */ - .align 3 - bal 1f - nop - .dword _gp -1: - ld gp, 0(ra) - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - /* Initialize any external memory */ - dla t9, lowlevel_init - jalr t9 - nop - - /* Initialize caches... */ - dla t9, mips_cache_reset - jalr t9 - nop - - /* ... and enable them */ - dli t0, CONFIG_SYS_MIPS_CACHE_MODE - mtc0 t0, CP0_CONFIG -#endif - - /* Set up temporary stack */ - dli t0, -16 - dli t1, CONFIG_SYS_INIT_SP_ADDR - and sp, t1, t0 # force 16 byte alignment - dsub sp, sp, GD_SIZE # reserve space for gd - and sp, sp, t0 # force 16 byte alignment - move k0, sp # save gd pointer -#ifdef CONFIG_SYS_MALLOC_F_LEN - dli t2, CONFIG_SYS_MALLOC_F_LEN - dsub sp, sp, t2 # reserve space for early malloc - and sp, sp, t0 # force 16 byte alignment -#endif - move fp, sp - - /* Clear gd */ - move t0, k0 -1: - sw zero, 0(t0) - blt t0, t1, 1b - daddi t0, 4 - -#ifdef CONFIG_SYS_MALLOC_F_LEN - daddu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset - sw sp, 0(t0) -#endif - - dla t9, board_init_f - jr t9 - move ra, zero - -/* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. - * - * a0 = addr_sp - * a1 = gd - * a2 = destination address - */ - .globl relocate_code - .ent relocate_code -relocate_code: - move sp, a0 # set new stack pointer - move fp, sp - - move s0, a1 # save gd in s0 - move s2, a2 # save destination address in s2 - - dli t0, CONFIG_SYS_MONITOR_BASE - dsub s1, s2, t0 # s1 <-- relocation offset - - dla t3, in_ram - ld t2, -24(t3) # t2 <-- __image_copy_end - move t1, a2 - - dadd gp, s1 # adjust gp - - /* - * t0 = source address - * t1 = target address - * t2 = source end address - */ -1: - lw t3, 0(t0) - sw t3, 0(t1) - daddu t0, 4 - blt t0, t2, 1b - daddu t1, 4 - - /* If caches were enabled, we would have to flush them here. */ - dsub a1, t1, s2 # a1 <-- size - dla t9, flush_cache - jalr t9 - move a0, s2 # a0 <-- destination address - - /* Jump to where we've relocated ourselves */ - daddi t0, s2, in_ram - _start - jr t0 - nop - - .dword __rel_dyn_end - .dword __rel_dyn_start - .dword __image_copy_end - .dword _GLOBAL_OFFSET_TABLE_ - .dword num_got_entries - -in_ram: - /* - * Now we want to update GOT. - * - * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object - * generated by GNU ld. Skip these reserved entries from relocation. - */ - ld t3, -8(t0) # t3 <-- num_got_entries - ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ - dadd t8, s1 # t8 now holds relocated _G_O_T_ - daddi t8, t8, 16 # skipping first two entries - dli t2, 2 -1: - ld t1, 0(t8) - beqz t1, 2f - dadd t1, s1 - sd t1, 0(t8) -2: - daddi t2, 1 - blt t2, t3, 1b - daddi t8, 8 - - /* Update dynamic relocations */ - ld t1, -32(t0) # t1 <-- __rel_dyn_start - ld t2, -40(t0) # t2 <-- __rel_dyn_end - - b 2f # skip first reserved entry - daddi t1, 16 - -1: - lw t8, -4(t1) # t8 <-- relocation info - - dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) - bne t8, t3, 2f # skip non R_MIPS_REL32 entries - nop - - ld t3, -16(t1) # t3 <-- location to fix up in FLASH - - ld t8, 0(t3) # t8 <-- original pointer - dadd t8, s1 # t8 <-- adjusted pointer - - dadd t3, s1 # t3 <-- location to fix up in RAM - sd t8, 0(t3) - -2: - blt t1, t2, 1b - daddi t1, 16 # each rel.dyn entry is 16 bytes - - /* - * Clear BSS - * - * GOT is now relocated. Thus __bss_start and __bss_end can be - * accessed directly via $gp. - */ - dla t1, __bss_start # t1 <-- __bss_start - dla t2, __bss_end # t2 <-- __bss_end - -1: - sd zero, 0(t1) - blt t1, t2, 1b - daddi t1, 8 - - move a0, s0 # a0 <-- gd - move a1, s2 - dla t9, board_init_r - jr t9 - move ra, zero - - .end relocate_code diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c deleted file mode 100644 index 553da5f..0000000 --- a/arch/mips/cpu/mips64/time.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -unsigned long notrace timer_read_counter(void) -{ - return read_c0_count(); -} - -ulong notrace get_tbclk(void) -{ - return CONFIG_SYS_MIPS_TIMER_FREQ; -} diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/start.S similarity index 100% rename from arch/mips/cpu/mips32/start.S rename to arch/mips/cpu/start.S diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/time.c similarity index 100% rename from arch/mips/cpu/mips32/time.c rename to arch/mips/cpu/time.c