diff mbox

[U-Boot] odroid: fix g2d sclk rate

Message ID 1422001807-1515-1-git-send-email-jy0922.shim@samsung.com
State Accepted
Delegated to: Minkyu Kang
Headers show

Commit Message

Joonyoung Shim Jan. 23, 2015, 8:30 a.m. UTC
G2D core should be provided 200MHz clock rate.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
---
 board/samsung/odroid/odroid.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Minkyu Kang Feb. 13, 2015, 8:25 a.m. UTC | #1
On 23/01/15 17:30, Joonyoung Shim wrote:
> G2D core should be provided 200MHz clock rate.
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> ---
>  board/samsung/odroid/odroid.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
> index b7d2381..1554b9d 100644
> --- a/board/samsung/odroid/odroid.c
> +++ b/board/samsung/odroid/odroid.c
> @@ -248,12 +248,12 @@ static void board_clock_init(void)
>  	 * MOUTc2c = 800 Mhz
>  	 * MOUTpwi = 108 MHz
>  	 *
> -	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
> +	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
>  	 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
>  	 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
>  	 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
>  	 */
> -	set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
> +	set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
>  	      C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
>  
>  	clrsetbits_le32(&clk->div_dmc1, clr, set);
> 

applied to u-boot-samsung.

Thank,
Minkyu Kang.
diff mbox

Patch

diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index b7d2381..1554b9d 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -248,12 +248,12 @@  static void board_clock_init(void)
 	 * MOUTc2c = 800 Mhz
 	 * MOUTpwi = 108 MHz
 	 *
-	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
+	 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
 	 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
 	 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
 	 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
 	 */
-	set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
+	set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
 	      C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
 
 	clrsetbits_le32(&clk->div_dmc1, clr, set);