From patchwork Fri Jan 9 03:30:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 426903 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E52CA14012F for ; Fri, 9 Jan 2015 14:32:24 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3830E4B654; Fri, 9 Jan 2015 04:32:09 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ec5dvQhguWCO; Fri, 9 Jan 2015 04:32:09 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 965DA4B672; Fri, 9 Jan 2015 04:31:47 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2F9244B5E9 for ; Fri, 9 Jan 2015 04:31:36 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id IFoCx5k7yrbf for ; Fri, 9 Jan 2015 04:31:36 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yk0-f202.google.com (mail-yk0-f202.google.com [209.85.160.202]) by theia.denx.de (Postfix) with ESMTPS id 14D424B604 for ; Fri, 9 Jan 2015 04:31:30 +0100 (CET) Received: by mail-yk0-f202.google.com with SMTP id 9so465614ykp.1 for ; Thu, 08 Jan 2015 19:31:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mM8PXA+vdSjaKUKgEKSFcTC6cqyFbxCiIApeN92T7bw=; b=j2Juj5hvpzkp4w9w7Cw09JGG7kI37FA75qTfjzN2ILhT/TGO2ChBZzjGT3Juwp5OiT JMuIF+2LA2rumUjQEzAOKaojgkrQIiTB8SST2sI5i1zupgd7mjwHu5LZ0QKhXfjmT/DX xiDLQuF3QLXFzDRDiYmmWGwSJTJwhxtO1gn0H6efzbPz+bohWCBoK6nsCIbo5KsCQb5m LEEDpgkNyeWRTEyAxz/nt1AQdDqbNDoi8KJp+frKt/PwbQQPaCI7n1CMh5ohrn0P86dt 3ogkTH7g/0h6Q0fCpIzmwgjIFj7x3FQCHyxjO67WPmUx5dELg13BWJqifPome+oAaoeB Dd5w== X-Gm-Message-State: ALoCoQnZJDpro4+Dw58cEJSK/9DsupNtxTDW4SHUVg9OaFNk19yNovwOW6bqCymeDt11p7Ht7GTZ X-Received: by 10.236.67.38 with SMTP id i26mr9573771yhd.26.1420774288732; Thu, 08 Jan 2015 19:31:28 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id r25si93680yhf.2.2015.01.08.19.31.28 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Jan 2015 19:31:28 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id PdCPsENl.1; Thu, 08 Jan 2015 19:31:28 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id DA434220325; Thu, 8 Jan 2015 20:31:27 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 8 Jan 2015 20:30:53 -0700 Message-Id: <1420774255-702-10-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1420774255-702-1-git-send-email-sjg@chromium.org> References: <1420774255-702-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH v2 09/11] x86: config: Enable hook for saving MRC configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass --- Changes in v2: None include/configs/chromebook_link.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 7e6d239..6e8b9ef 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -20,6 +20,7 @@ #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R #define CONFIG_NR_DRAM_BANKS 8 #define CONFIG_X86_MRC_ADDR 0xfffa0000