From patchwork Wed Dec 24 19:06:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 423987 X-Patchwork-Delegate: ijc@hellion.org.uk Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 150D314009B for ; Thu, 25 Dec 2014 06:08:04 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 287AB4B659; Wed, 24 Dec 2014 20:07:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id sTnaQgkys4SM; Wed, 24 Dec 2014 20:07:41 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6D4DD4B61F; Wed, 24 Dec 2014 20:07:09 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 04B5F4B604 for ; Wed, 24 Dec 2014 20:06:51 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PozEIVzSowUF for ; Wed, 24 Dec 2014 20:06:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by theia.denx.de (Postfix) with ESMTPS id 548574B60B for ; Wed, 24 Dec 2014 20:06:50 +0100 (CET) Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id sBOJ6huq032663 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 24 Dec 2014 14:06:44 -0500 Received: from shalem.localdomain.com (vpn1-6-156.ams2.redhat.com [10.36.6.156]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id sBOJ6UXd006510; Wed, 24 Dec 2014 14:06:42 -0500 From: Hans de Goede To: Ian Campbell Date: Wed, 24 Dec 2014 20:06:20 +0100 Message-Id: <1419447989-21959-9-git-send-email-hdegoede@redhat.com> In-Reply-To: <1419447989-21959-1-git-send-email-hdegoede@redhat.com> References: <1419447989-21959-1-git-send-email-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 08/17] sunxi: video: Move sunxi_drc_init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Move sunxi_drc_init to directly above sunxi_engines_init, to avoid unnecessary Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/video/sunxi_display.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index aed6ae6..ea7548b 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -472,18 +472,6 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double); } -#ifdef CONFIG_MACH_SUN6I -static void sunxi_drc_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* On sun6i the drc must be clocked even when in pass-through mode */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); - clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); -} -#endif - static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode) { struct sunxi_hdmi_reg * const hdmi = @@ -592,13 +580,23 @@ static void sunxi_hdmi_enable(void) setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE); } +static void sunxi_drc_init(void) +{ +#ifdef CONFIG_MACH_SUN6I + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* On sun6i the drc must be clocked even when in pass-through mode */ + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); + clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); +#endif +} + static void sunxi_engines_init(void) { sunxi_composer_init(); sunxi_lcdc_init(); -#ifdef CONFIG_MACH_SUN6I sunxi_drc_init(); -#endif } static void sunxi_mode_set(const struct ctfb_res_modes *mode,