| Message ID | 1418761900-14035-2-git-send-email-hdegoede@redhat.com |
|---|---|
| State | Superseded |
| Delegated to: | Ian Campbell |
| Headers | show |
Hi, On Wed, Dec 17, 2014 at 4:31 AM, Hans de Goede <hdegoede@redhat.com> wrote: > sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, > the rsb is also used to communicate with the pmic on the A80, and is > documented in the A80 user manual. > > This commit adds support for this based on the rsb driver from the allwinner > u-boot sources. > > Note: Not yet ready for upstream, code needs some significant cleanups. Confusing note. > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > arch/arm/cpu/armv7/sunxi/Makefile | 1 + > arch/arm/cpu/armv7/sunxi/rsb.c | 158 +++++++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-sunxi/cpu.h | 3 +- > arch/arm/include/asm/arch-sunxi/gpio.h | 2 + > arch/arm/include/asm/arch-sunxi/prcm.h | 3 +- > arch/arm/include/asm/arch-sunxi/rsb.h | 55 ++++++++++++ > 6 files changed, 220 insertions(+), 2 deletions(-) > create mode 100644 arch/arm/cpu/armv7/sunxi/rsb.c > create mode 100644 arch/arm/include/asm/arch-sunxi/rsb.h > > diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile > index 1337b60..3e8975a 100644 > --- a/arch/arm/cpu/armv7/sunxi/Makefile > +++ b/arch/arm/cpu/armv7/sunxi/Makefile > @@ -15,6 +15,7 @@ obj-y += pinmux.o > obj-$(CONFIG_MACH_SUN6I) += prcm.o > obj-$(CONFIG_MACH_SUN8I) += prcm.o > obj-$(CONFIG_MACH_SUN6I) += p2wi.o > +obj-$(CONFIG_MACH_SUN8I) += rsb.o > obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o > obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o > obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o > diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c > new file mode 100644 > index 0000000..b72bb9d > --- /dev/null > +++ b/arch/arm/cpu/armv7/sunxi/rsb.c > @@ -0,0 +1,158 @@ > +/* > + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> > + * > + * Based on allwinner u-boot sources rsb code which is: > + * (C) Copyright 2007-2013 > + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> > + * lixiang <lixiang@allwinnertech.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <errno.h> > +#include <asm/arch/cpu.h> > +#include <asm/arch/gpio.h> > +#include <asm/arch/prcm.h> > +#include <asm/arch/rsb.h> > + > +static void rsb_cfg_io(void) > +{ > + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK); > + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA); > + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); > + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); > + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); > + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); > +} > + > +static void rsb_set_clk(void) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + u32 div = 0; > + u32 cd_odly = 0; > + > + /* Source is Hosc24M, set RSB clk to 3Mhz */ > + div = 24000000 / 3000000 / 2 - 1; > + cd_odly = div >> 1; > + if (!cd_odly) > + cd_odly = 1; > + > + writel((cd_odly << 8) | div, &rsb->ccr); > +} > + > +void rsb_init(void) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + > + rsb_cfg_io(); > + > + /* Enable RSB and PIO clk, and de-assert their resets */ > + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); > + > + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); Do we need a small delay here for the device to finish reset? > + rsb_set_clk(); > +} > + > +static int rsb_await_trans(void) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + unsigned long tmo = timer_get_us() + 1000000; > + u32 stat; > + int ret; > + > + while (1) { > + stat = readl(&rsb->stat); > + if (stat & RSB_STAT_LBSY_INT) { > + ret = -EBUSY; > + break; > + } > + if (stat & RSB_STAT_TERR_INT) { > + ret = -EIO; > + break; > + } > + if (stat & RSB_STAT_TOVER_INT) { > + ret = 0; > + break; > + } > + if (timer_get_us() > tmo) { > + ret = -ETIME; > + break; > + } > + } > + writel(stat, &rsb->stat); /* Clear status bits */ > + > + return ret; > +} > + > +int rsb_set_device_mode(u32 device_mode_data) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + unsigned long tmo = timer_get_us() + 1000000; > + > + writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr); > + > + while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { > + if (timer_get_us() > tmo) > + return -ETIME; > + } > + > + return rsb_await_trans(); > +} > + > +static int rsb_do_trans(void) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + > + setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); > + return rsb_await_trans(); > +} > + > +int rsb_set_device_address(u16 device_addr, u16 runtime_addr) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + > + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | > + RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); > + writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); > + > + return rsb_do_trans(); > +} > + > +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + > + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); > + writel(reg_addr, &rsb->addr); > + writel(data, &rsb->data); > + writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); > + > + return rsb_do_trans(); > +} > + > +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) > +{ > + struct sunxi_rsb_reg * const rsb = > + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; > + int ret; > + > + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); > + writel(reg_addr, &rsb->addr); > + writel(RSB_CMD_BYTE_READ, &rsb->cmd); > + > + ret = rsb_do_trans(); > + if (ret) > + return ret; > + > + *data = readl(&rsb->data) & 0xff; > + > + return 0; > +} > diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h > index 9500262..49c1614 100644 > --- a/arch/arm/include/asm/arch-sunxi/cpu.h > +++ b/arch/arm/include/asm/arch-sunxi/cpu.h > @@ -128,7 +128,8 @@ > #define SUN6I_CPUCFG_BASE 0x01f01c00 > #define SUNXI_R_UART_BASE 0x01f02800 > #define SUNXI_R_PIO_BASE 0x01f02c00 > -#define SUNXI_P2WI_BASE 0x01f03400 > +#define SUNXI_P2WI_BASE 0x01f03400 /* on sun6i */ > +#define SUNXI_RSB_BASE 0x01f03400 /* on sun8i */ Maybe we just use SUN6I_ SUN8I_ prefixes? The base address will be different on sun9i. > > /* CoreSight Debug Module */ > #define SUNXI_CSDM_BASE 0x3f500000 > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index 9f972ce..6623f15 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -176,6 +176,8 @@ enum sunxi_gpio_number { > #define SUN6I_GPL0_R_P2WI_SCK 3 > #define SUN6I_GPL1_R_P2WI_SDA 3 > > +#define SUN8I_GPL0_R_RSB_SCK 2 > +#define SUN8I_GPL1_R_RSB_SDA 2 > #define SUN8I_GPL2_R_UART_TX 2 > #define SUN8I_GPL3_R_UART_RX 2 > > diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h > index 88de1ff..82ed541 100644 > --- a/arch/arm/include/asm/arch-sunxi/prcm.h > +++ b/arch/arm/include/asm/arch-sunxi/prcm.h > @@ -50,7 +50,8 @@ > #define PRCM_APB0_GATE_PIO (0x1 << 0) > #define PRCM_APB0_GATE_IR (0x1 << 1) > #define PRCM_APB0_GATE_TIMER01 (0x1 << 2) > -#define PRCM_APB0_GATE_P2WI (0x1 << 3) > +#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ > +#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ > #define PRCM_APB0_GATE_UART (0x1 << 4) > #define PRCM_APB0_GATE_1WIRE (0x1 << 5) > #define PRCM_APB0_GATE_I2C (0x1 << 6) > diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h > new file mode 100644 > index 0000000..95a595a > --- /dev/null > +++ b/arch/arm/include/asm/arch-sunxi/rsb.h > @@ -0,0 +1,55 @@ > +/* > + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> > + * > + * Based on allwinner u-boot sources rsb code which is: > + * (C) Copyright 2007-2013 > + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> > + * lixiang <lixiang@allwinnertech.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __SUNXI_RSB_H > +#define __SUNXI_RSB_H > + > +#include <common.h> > +#include <asm/io.h> > + > +struct sunxi_rsb_reg { > + u32 ctrl; /* 0x00 */ > + u32 ccr; /* 0x04 */ > + u32 inte; /* 0x08 */ > + u32 stat; /* 0x0c */ > + u32 addr; /* 0x10 */ > + u8 res0[8]; /* 0x14 */ > + u32 data; /* 0x1c */ > + u8 res1[4]; /* 0x20 */ > + u32 lcr; /* 0x24 */ > + u32 dmcr; /* 0x28 */ > + u32 cmd; /* 0x2c */ > + u32 devaddr; /* 0x30 */ > +}; > + > +#define RSB_CTRL_SOFT_RST (1 << 0) > +#define RSB_CTRL_START_TRANS (1 << 7) > + > +#define RSB_STAT_TOVER_INT (1 << 0) > +#define RSB_STAT_TERR_INT (1 << 1) > +#define RSB_STAT_LBSY_INT (1 << 2) > + > +#define RSB_DMCR_DEVICE_MODE_START (1 << 31) > + > +#define RSB_CMD_BYTE_WRITE 0x4e > +#define RSB_CMD_BYTE_READ 0x8b > +#define RSB_CMD_SET_RTSADDR 0xe8 > + > +#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16) > +#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0) > + > +void rsb_init(void); > +int rsb_set_device_mode(u32 device_mode_data); > +int rsb_set_device_address(u16 device_addr, u16 runtime_addr); > +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data); > +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data); > + > +#endif > -- > 2.1.0 The rest looks good. Thanks! ChenYu
Hi, On 17-12-14 03:22, Chen-Yu Tsai wrote: > Hi, > > On Wed, Dec 17, 2014 at 4:31 AM, Hans de Goede <hdegoede@redhat.com> wrote: >> sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, >> the rsb is also used to communicate with the pmic on the A80, and is >> documented in the A80 user manual. >> >> This commit adds support for this based on the rsb driver from the allwinner >> u-boot sources. >> >> Note: Not yet ready for upstream, code needs some significant cleanups. > > Confusing note. Ugh, I forgot to remove that note after doing the cleanups, I'll remove it from the version of the patch my personal tree :) > >> >> Signed-off-by: Hans de Goede <hdegoede@redhat.com> >> --- >> arch/arm/cpu/armv7/sunxi/Makefile | 1 + >> arch/arm/cpu/armv7/sunxi/rsb.c | 158 +++++++++++++++++++++++++++++++++ >> arch/arm/include/asm/arch-sunxi/cpu.h | 3 +- >> arch/arm/include/asm/arch-sunxi/gpio.h | 2 + >> arch/arm/include/asm/arch-sunxi/prcm.h | 3 +- >> arch/arm/include/asm/arch-sunxi/rsb.h | 55 ++++++++++++ >> 6 files changed, 220 insertions(+), 2 deletions(-) >> create mode 100644 arch/arm/cpu/armv7/sunxi/rsb.c >> create mode 100644 arch/arm/include/asm/arch-sunxi/rsb.h >> >> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile >> index 1337b60..3e8975a 100644 >> --- a/arch/arm/cpu/armv7/sunxi/Makefile >> +++ b/arch/arm/cpu/armv7/sunxi/Makefile >> @@ -15,6 +15,7 @@ obj-y += pinmux.o >> obj-$(CONFIG_MACH_SUN6I) += prcm.o >> obj-$(CONFIG_MACH_SUN8I) += prcm.o >> obj-$(CONFIG_MACH_SUN6I) += p2wi.o >> +obj-$(CONFIG_MACH_SUN8I) += rsb.o >> obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o >> obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o >> obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o >> diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c >> new file mode 100644 >> index 0000000..b72bb9d >> --- /dev/null >> +++ b/arch/arm/cpu/armv7/sunxi/rsb.c >> @@ -0,0 +1,158 @@ >> +/* >> + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> >> + * >> + * Based on allwinner u-boot sources rsb code which is: >> + * (C) Copyright 2007-2013 >> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> >> + * lixiang <lixiang@allwinnertech.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <errno.h> >> +#include <asm/arch/cpu.h> >> +#include <asm/arch/gpio.h> >> +#include <asm/arch/prcm.h> >> +#include <asm/arch/rsb.h> >> + >> +static void rsb_cfg_io(void) >> +{ >> + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK); >> + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA); >> + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); >> + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); >> + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); >> + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); >> +} >> + >> +static void rsb_set_clk(void) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + u32 div = 0; >> + u32 cd_odly = 0; >> + >> + /* Source is Hosc24M, set RSB clk to 3Mhz */ >> + div = 24000000 / 3000000 / 2 - 1; >> + cd_odly = div >> 1; >> + if (!cd_odly) >> + cd_odly = 1; >> + >> + writel((cd_odly << 8) | div, &rsb->ccr); >> +} >> + >> +void rsb_init(void) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + >> + rsb_cfg_io(); >> + >> + /* Enable RSB and PIO clk, and de-assert their resets */ >> + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); >> + >> + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); > > Do we need a small delay here for the device to finish reset? Maybe, this (no delay) is what the allwinner code was doing, and it seems to work fine ... > >> + rsb_set_clk(); >> +} >> + >> +static int rsb_await_trans(void) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + unsigned long tmo = timer_get_us() + 1000000; >> + u32 stat; >> + int ret; >> + >> + while (1) { >> + stat = readl(&rsb->stat); >> + if (stat & RSB_STAT_LBSY_INT) { >> + ret = -EBUSY; >> + break; >> + } >> + if (stat & RSB_STAT_TERR_INT) { >> + ret = -EIO; >> + break; >> + } >> + if (stat & RSB_STAT_TOVER_INT) { >> + ret = 0; >> + break; >> + } >> + if (timer_get_us() > tmo) { >> + ret = -ETIME; >> + break; >> + } >> + } >> + writel(stat, &rsb->stat); /* Clear status bits */ >> + >> + return ret; >> +} >> + >> +int rsb_set_device_mode(u32 device_mode_data) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + unsigned long tmo = timer_get_us() + 1000000; >> + >> + writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr); >> + >> + while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { >> + if (timer_get_us() > tmo) >> + return -ETIME; >> + } >> + >> + return rsb_await_trans(); >> +} >> + >> +static int rsb_do_trans(void) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + >> + setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); >> + return rsb_await_trans(); >> +} >> + >> +int rsb_set_device_address(u16 device_addr, u16 runtime_addr) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + >> + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | >> + RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); >> + writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); >> + >> + return rsb_do_trans(); >> +} >> + >> +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + >> + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); >> + writel(reg_addr, &rsb->addr); >> + writel(data, &rsb->data); >> + writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); >> + >> + return rsb_do_trans(); >> +} >> + >> +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) >> +{ >> + struct sunxi_rsb_reg * const rsb = >> + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; >> + int ret; >> + >> + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); >> + writel(reg_addr, &rsb->addr); >> + writel(RSB_CMD_BYTE_READ, &rsb->cmd); >> + >> + ret = rsb_do_trans(); >> + if (ret) >> + return ret; >> + >> + *data = readl(&rsb->data) & 0xff; >> + >> + return 0; >> +} >> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h >> index 9500262..49c1614 100644 >> --- a/arch/arm/include/asm/arch-sunxi/cpu.h >> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h >> @@ -128,7 +128,8 @@ >> #define SUN6I_CPUCFG_BASE 0x01f01c00 >> #define SUNXI_R_UART_BASE 0x01f02800 >> #define SUNXI_R_PIO_BASE 0x01f02c00 >> -#define SUNXI_P2WI_BASE 0x01f03400 >> +#define SUNXI_P2WI_BASE 0x01f03400 /* on sun6i */ >> +#define SUNXI_RSB_BASE 0x01f03400 /* on sun8i */ > > Maybe we just use SUN6I_ SUN8I_ prefixes? > The base address will be different on sun9i. > >> >> /* CoreSight Debug Module */ >> #define SUNXI_CSDM_BASE 0x3f500000 >> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h >> index 9f972ce..6623f15 100644 >> --- a/arch/arm/include/asm/arch-sunxi/gpio.h >> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h >> @@ -176,6 +176,8 @@ enum sunxi_gpio_number { >> #define SUN6I_GPL0_R_P2WI_SCK 3 >> #define SUN6I_GPL1_R_P2WI_SDA 3 >> >> +#define SUN8I_GPL0_R_RSB_SCK 2 >> +#define SUN8I_GPL1_R_RSB_SDA 2 >> #define SUN8I_GPL2_R_UART_TX 2 >> #define SUN8I_GPL3_R_UART_RX 2 >> >> diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h >> index 88de1ff..82ed541 100644 >> --- a/arch/arm/include/asm/arch-sunxi/prcm.h >> +++ b/arch/arm/include/asm/arch-sunxi/prcm.h >> @@ -50,7 +50,8 @@ >> #define PRCM_APB0_GATE_PIO (0x1 << 0) >> #define PRCM_APB0_GATE_IR (0x1 << 1) >> #define PRCM_APB0_GATE_TIMER01 (0x1 << 2) >> -#define PRCM_APB0_GATE_P2WI (0x1 << 3) >> +#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ >> +#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ >> #define PRCM_APB0_GATE_UART (0x1 << 4) >> #define PRCM_APB0_GATE_1WIRE (0x1 << 5) >> #define PRCM_APB0_GATE_I2C (0x1 << 6) >> diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h >> new file mode 100644 >> index 0000000..95a595a >> --- /dev/null >> +++ b/arch/arm/include/asm/arch-sunxi/rsb.h >> @@ -0,0 +1,55 @@ >> +/* >> + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> >> + * >> + * Based on allwinner u-boot sources rsb code which is: >> + * (C) Copyright 2007-2013 >> + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> >> + * lixiang <lixiang@allwinnertech.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#ifndef __SUNXI_RSB_H >> +#define __SUNXI_RSB_H >> + >> +#include <common.h> >> +#include <asm/io.h> >> + >> +struct sunxi_rsb_reg { >> + u32 ctrl; /* 0x00 */ >> + u32 ccr; /* 0x04 */ >> + u32 inte; /* 0x08 */ >> + u32 stat; /* 0x0c */ >> + u32 addr; /* 0x10 */ >> + u8 res0[8]; /* 0x14 */ >> + u32 data; /* 0x1c */ >> + u8 res1[4]; /* 0x20 */ >> + u32 lcr; /* 0x24 */ >> + u32 dmcr; /* 0x28 */ >> + u32 cmd; /* 0x2c */ >> + u32 devaddr; /* 0x30 */ >> +}; >> + >> +#define RSB_CTRL_SOFT_RST (1 << 0) >> +#define RSB_CTRL_START_TRANS (1 << 7) >> + >> +#define RSB_STAT_TOVER_INT (1 << 0) >> +#define RSB_STAT_TERR_INT (1 << 1) >> +#define RSB_STAT_LBSY_INT (1 << 2) >> + >> +#define RSB_DMCR_DEVICE_MODE_START (1 << 31) >> + >> +#define RSB_CMD_BYTE_WRITE 0x4e >> +#define RSB_CMD_BYTE_READ 0x8b >> +#define RSB_CMD_SET_RTSADDR 0xe8 >> + >> +#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16) >> +#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0) >> + >> +void rsb_init(void); >> +int rsb_set_device_mode(u32 device_mode_data); >> +int rsb_set_device_address(u16 device_addr, u16 runtime_addr); >> +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data); >> +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data); >> + >> +#endif >> -- >> 2.1.0 > > The rest looks good. Thanks! Regards, Hans
On Wed, 2014-12-17 at 13:56 +0100, Hans de Goede wrote: > Hi, > > On 17-12-14 03:22, Chen-Yu Tsai wrote: > > Hi, > > > > On Wed, Dec 17, 2014 at 4:31 AM, Hans de Goede <hdegoede@redhat.com> wrote: > >> sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, > >> the rsb is also used to communicate with the pmic on the A80, and is > >> documented in the A80 user manual. > >> > >> This commit adds support for this based on the rsb driver from the allwinner > >> u-boot sources. > >> > >> Note: Not yet ready for upstream, code needs some significant cleanups. > > > > Confusing note. > > Ugh, I forgot to remove that note after doing the cleanups, I'll remove it > from the version of the patch my personal tree :) I'll stop ignoring this patch then ;-) Ian.
On Wed, 2014-12-17 at 13:56 +0100, Hans de Goede wrote: > >> @@ -128,7 +128,8 @@ > >> #define SUN6I_CPUCFG_BASE 0x01f01c00 > >> #define SUNXI_R_UART_BASE 0x01f02800 > >> #define SUNXI_R_PIO_BASE 0x01f02c00 > >> -#define SUNXI_P2WI_BASE 0x01f03400 > >> +#define SUNXI_P2WI_BASE 0x01f03400 /* on sun6i */ > >> +#define SUNXI_RSB_BASE 0x01f03400 /* on sun8i */ > > > > Maybe we just use SUN6I_ SUN8I_ prefixes? > > The base address will be different on sun9i. Did you miss this suggestions from Chen-Yu? Seems like a good one. I don't have any other comments. Ian.
Hi, On 18-12-14 19:59, Ian Campbell wrote: > On Wed, 2014-12-17 at 13:56 +0100, Hans de Goede wrote: >>>> @@ -128,7 +128,8 @@ >>>> #define SUN6I_CPUCFG_BASE 0x01f01c00 >>>> #define SUNXI_R_UART_BASE 0x01f02800 >>>> #define SUNXI_R_PIO_BASE 0x01f02c00 >>>> -#define SUNXI_P2WI_BASE 0x01f03400 >>>> +#define SUNXI_P2WI_BASE 0x01f03400 /* on sun6i */ >>>> +#define SUNXI_RSB_BASE 0x01f03400 /* on sun8i */ >>> >>> Maybe we just use SUN6I_ SUN8I_ prefixes? >>> The base address will be different on sun9i. > > Did you miss this suggestions from Chen-Yu? Seems like a good one. Yes I missed that (must have read over it). That will work for P2Wi, but not for RSB, as RSB is used on the A80 too AFAIK, but I guess having P2WI as SUN6I and RSB as SUNXI makes it clear what is used where, so I'll update the patch with that change. Regards, Hans
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 1337b60..3e8975a 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -15,6 +15,7 @@ obj-y += pinmux.o obj-$(CONFIG_MACH_SUN6I) += prcm.o obj-$(CONFIG_MACH_SUN8I) += prcm.o obj-$(CONFIG_MACH_SUN6I) += p2wi.o +obj-$(CONFIG_MACH_SUN8I) += rsb.o obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c new file mode 100644 index 0000000..b72bb9d --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/rsb.c @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * Based on allwinner u-boot sources rsb code which is: + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * lixiang <lixiang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/prcm.h> +#include <asm/arch/rsb.h> + +static void rsb_cfg_io(void) +{ + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA); + sunxi_gpio_set_pull(SUNXI_GPL(0), 1); + sunxi_gpio_set_pull(SUNXI_GPL(1), 1); + sunxi_gpio_set_drv(SUNXI_GPL(0), 2); + sunxi_gpio_set_drv(SUNXI_GPL(1), 2); +} + +static void rsb_set_clk(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + u32 div = 0; + u32 cd_odly = 0; + + /* Source is Hosc24M, set RSB clk to 3Mhz */ + div = 24000000 / 3000000 / 2 - 1; + cd_odly = div >> 1; + if (!cd_odly) + cd_odly = 1; + + writel((cd_odly << 8) | div, &rsb->ccr); +} + +void rsb_init(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + rsb_cfg_io(); + + /* Enable RSB and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); + rsb_set_clk(); +} + +static int rsb_await_trans(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + unsigned long tmo = timer_get_us() + 1000000; + u32 stat; + int ret; + + while (1) { + stat = readl(&rsb->stat); + if (stat & RSB_STAT_LBSY_INT) { + ret = -EBUSY; + break; + } + if (stat & RSB_STAT_TERR_INT) { + ret = -EIO; + break; + } + if (stat & RSB_STAT_TOVER_INT) { + ret = 0; + break; + } + if (timer_get_us() > tmo) { + ret = -ETIME; + break; + } + } + writel(stat, &rsb->stat); /* Clear status bits */ + + return ret; +} + +int rsb_set_device_mode(u32 device_mode_data) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + unsigned long tmo = timer_get_us() + 1000000; + + writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr); + + while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) { + if (timer_get_us() > tmo) + return -ETIME; + } + + return rsb_await_trans(); +} + +static int rsb_do_trans(void) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS); + return rsb_await_trans(); +} + +int rsb_set_device_address(u16 device_addr, u16 runtime_addr) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) | + RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr); + writel(RSB_CMD_SET_RTSADDR, &rsb->cmd); + + return rsb_do_trans(); +} + +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); + writel(reg_addr, &rsb->addr); + writel(data, &rsb->data); + writel(RSB_CMD_BYTE_WRITE, &rsb->cmd); + + return rsb_do_trans(); +} + +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) +{ + struct sunxi_rsb_reg * const rsb = + (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; + int ret; + + writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr); + writel(reg_addr, &rsb->addr); + writel(RSB_CMD_BYTE_READ, &rsb->cmd); + + ret = rsb_do_trans(); + if (ret) + return ret; + + *data = readl(&rsb->data) & 0xff; + + return 0; +} diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 9500262..49c1614 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -128,7 +128,8 @@ #define SUN6I_CPUCFG_BASE 0x01f01c00 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUNXI_P2WI_BASE 0x01f03400 +#define SUNXI_P2WI_BASE 0x01f03400 /* on sun6i */ +#define SUNXI_RSB_BASE 0x01f03400 /* on sun8i */ /* CoreSight Debug Module */ #define SUNXI_CSDM_BASE 0x3f500000 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 9f972ce..6623f15 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -176,6 +176,8 @@ enum sunxi_gpio_number { #define SUN6I_GPL0_R_P2WI_SCK 3 #define SUN6I_GPL1_R_P2WI_SDA 3 +#define SUN8I_GPL0_R_RSB_SCK 2 +#define SUN8I_GPL1_R_RSB_SDA 2 #define SUN8I_GPL2_R_UART_TX 2 #define SUN8I_GPL3_R_UART_RX 2 diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 88de1ff..82ed541 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -50,7 +50,8 @@ #define PRCM_APB0_GATE_PIO (0x1 << 0) #define PRCM_APB0_GATE_IR (0x1 << 1) #define PRCM_APB0_GATE_TIMER01 (0x1 << 2) -#define PRCM_APB0_GATE_P2WI (0x1 << 3) +#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ +#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ #define PRCM_APB0_GATE_UART (0x1 << 4) #define PRCM_APB0_GATE_1WIRE (0x1 << 5) #define PRCM_APB0_GATE_I2C (0x1 << 6) diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h new file mode 100644 index 0000000..95a595a --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/rsb.h @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * Based on allwinner u-boot sources rsb code which is: + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * lixiang <lixiang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SUNXI_RSB_H +#define __SUNXI_RSB_H + +#include <common.h> +#include <asm/io.h> + +struct sunxi_rsb_reg { + u32 ctrl; /* 0x00 */ + u32 ccr; /* 0x04 */ + u32 inte; /* 0x08 */ + u32 stat; /* 0x0c */ + u32 addr; /* 0x10 */ + u8 res0[8]; /* 0x14 */ + u32 data; /* 0x1c */ + u8 res1[4]; /* 0x20 */ + u32 lcr; /* 0x24 */ + u32 dmcr; /* 0x28 */ + u32 cmd; /* 0x2c */ + u32 devaddr; /* 0x30 */ +}; + +#define RSB_CTRL_SOFT_RST (1 << 0) +#define RSB_CTRL_START_TRANS (1 << 7) + +#define RSB_STAT_TOVER_INT (1 << 0) +#define RSB_STAT_TERR_INT (1 << 1) +#define RSB_STAT_LBSY_INT (1 << 2) + +#define RSB_DMCR_DEVICE_MODE_START (1 << 31) + +#define RSB_CMD_BYTE_WRITE 0x4e +#define RSB_CMD_BYTE_READ 0x8b +#define RSB_CMD_SET_RTSADDR 0xe8 + +#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16) +#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0) + +void rsb_init(void); +int rsb_set_device_mode(u32 device_mode_data); +int rsb_set_device_address(u16 device_addr, u16 runtime_addr); +int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data); +int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data); + +#endif
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb, the rsb is also used to communicate with the pmic on the A80, and is documented in the A80 user manual. This commit adds support for this based on the rsb driver from the allwinner u-boot sources. Note: Not yet ready for upstream, code needs some significant cleanups. Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/rsb.c | 158 +++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 3 +- arch/arm/include/asm/arch-sunxi/gpio.h | 2 + arch/arm/include/asm/arch-sunxi/prcm.h | 3 +- arch/arm/include/asm/arch-sunxi/rsb.h | 55 ++++++++++++ 6 files changed, 220 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/rsb.c create mode 100644 arch/arm/include/asm/arch-sunxi/rsb.h