From patchwork Wed Dec 10 05:25:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 419421 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9670E140079 for ; Wed, 10 Dec 2014 16:35:17 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 468A54B6DF; Wed, 10 Dec 2014 06:35:16 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tJjYDfRw5SoQ; Wed, 10 Dec 2014 06:35:15 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9BB1B4B6B3; Wed, 10 Dec 2014 06:35:15 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C8DA04B6B3 for ; Wed, 10 Dec 2014 06:35:10 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cKQDXmuS4qKx for ; Wed, 10 Dec 2014 06:35:10 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qa0-f74.google.com (mail-qa0-f74.google.com [209.85.216.74]) by theia.denx.de (Postfix) with ESMTPS id 6EE334B686 for ; Wed, 10 Dec 2014 06:35:06 +0100 (CET) Received: by mail-qa0-f74.google.com with SMTP id i13so132324qae.3 for ; Tue, 09 Dec 2014 21:35:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Go90x7n+05heI3n9g2Tem40GlUqQqfXvZXmTwEthKq8=; b=fY9DesTN47r3NUtwIlzgFfjQilK91yKXkfn0uwtoBRrwurFcDsFP6Ajem1M6yx0RjS AnoMAZI8sC+D30bDh9lpXkimfPYRFsR5CeLLkXKm2TDKjt44LMM1/xJLUpwKgWMvrSVL C/TObM9rxLJEbxG05KS4s12weApBhNtNp33AG3TaJij12pQ1d57rt4e7x4NFeS305nMK m4XlenjFO0Cf8yQcm5jxWu7SRynZpzLTfolf/n3KmOlqC+yE5KDvxM1MkpoSktHQiAxC riOvHuhhbUH2+zawhjBgN1zODeVJQawLOsvsgnOI+XGYvGra3j1zXjER94RweV7jgQ+h zlvw== X-Gm-Message-State: ALoCoQkUvkn3RpffAch6sc00o4IF0CEIMQGkvF/pPiM3oVZ8m1r9NNHMq6iSlMxZcmn6SiFoy1/D X-Received: by 10.52.11.38 with SMTP id n6mr2234683vdb.3.1418189705575; Tue, 09 Dec 2014 21:35:05 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id 26si113986yhj.7.2014.12.09.21.35.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Dec 2014 21:35:05 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id gwaYdSNZ.1; Tue, 09 Dec 2014 21:35:05 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 5EB96220D0A; Tue, 9 Dec 2014 22:25:40 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Tue, 9 Dec 2014 22:25:20 -0700 Message-Id: <1418189127-27407-17-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c In-Reply-To: <1418189127-27407-1-git-send-email-sjg@chromium.org> References: <1418189127-27407-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren , Thierry Reding Subject: [U-Boot] [PATCH v4 16/23] ARM: tegra: Add Tegra124 PCIe device tree node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Thierry Reding Add the device tree node for the PCIe controller found on Tegra124 SoCs. Acked-by: Stephen Warren Signed-off-by: Thierry Reding Signed-off-by: Simon Glass --- Changes in v4: None Changes in v3: None arch/arm/dts/tegra124.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index a899d54..9fa141d 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -10,6 +10,72 @@ compatible = "nvidia,tegra124"; interrupt-parent = <&gic>; + pcie-controller@01003000 { + compatible = "nvidia,tegra124-pcie"; + device_type = "pci"; + reg = <0x01003000 0x00000800 /* PADS registers */ + 0x01003800 0x00000800 /* AFI registers */ + 0x02000000 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = , /* controller interrupt */ + ; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; + phy-names = "pcie"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + gic: interrupt-controller@50041000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>;