diff mbox

[U-Boot,16/25] x86: Integrate Tunnel Creek processor microcode

Message ID 1417705366-19434-1-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng Dec. 4, 2014, 3:02 p.m. UTC 
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
 arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
 1 file changed, 1288 insertions(+)
 create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc

Comments

Simon Glass Dec. 4, 2014, 11:43 p.m. UTC | #1 
Hi Bin,

On 4 December 2014 at 08:02, Bin Meng <bmeng.cn@gmail.com> wrote:
> Integrate the processor microcode version 1.05 for Tunnel Creek,
> CPUID device 20661h.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
>  1 file changed, 1288 insertions(+)
>  create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc

Can we put this into the device tree?

Regards,
Simon
Bin Meng Dec. 5, 2014, 9:14 a.m. UTC | #2 
Hi Simon,

On Fri, Dec 5, 2014 at 7:43 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 4 December 2014 at 08:02, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Integrate the processor microcode version 1.05 for Tunnel Creek,
>> CPUID device 20661h.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>  arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
>>  1 file changed, 1288 insertions(+)
>>  create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc
>
> Can we put this into the device tree?
>

Unfortunately the microcode is required by the call to TempRamInit in
FSP in car_init, where the device tree functionality is not available.
We can of course duplicate one in device tree for reference, not sure
if it is necessary.

Regards,
Bin
Simon Glass Dec. 5, 2014, 3:12 p.m. UTC | #3 
Hi Bin,

On 5 December 2014 at 02:14, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Fri, Dec 5, 2014 at 7:43 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Bin,
>>
>> On 4 December 2014 at 08:02, Bin Meng <bmeng.cn@gmail.com> wrote:
>>> Integrate the processor microcode version 1.05 for Tunnel Creek,
>>> CPUID device 20661h.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>  arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
>>>  1 file changed, 1288 insertions(+)
>>>  create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc
>>
>> Can we put this into the device tree?
>>
>
> Unfortunately the microcode is required by the call to TempRamInit in
> FSP in car_init, where the device tree functionality is not available.
> We can of course duplicate one in device tree for reference, not sure
> if it is necessary.

OK I was hoping you weren't going to say that. There is not even a
stack at this stage so device tree is out of the question. I wonder
how common this is. Is there any way to provide a 'NULL'  microcode
update and then do it later?

This is some of the pain of dealing with binary blobs.

Let's see where this lands but we may want to change things around in
start.S to provide for this more nicely.

Regards,
Simon
Bin Meng Dec. 9, 2014, 2:39 p.m. UTC | #4 
Hi Simon,

On Fri, Dec 5, 2014 at 11:12 PM, Simon Glass <sjg@chromium.org> wrote:
> Hi Bin,
>
> On 5 December 2014 at 02:14, Bin Meng <bmeng.cn@gmail.com> wrote:
>> Hi Simon,
>>
>> On Fri, Dec 5, 2014 at 7:43 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Bin,
>>>
>>> On 4 December 2014 at 08:02, Bin Meng <bmeng.cn@gmail.com> wrote:
>>>> Integrate the processor microcode version 1.05 for Tunnel Creek,
>>>> CPUID device 20661h.
>>>>
>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>>> ---
>>>>  arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
>>>>  1 file changed, 1288 insertions(+)
>>>>  create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc
>>>
>>> Can we put this into the device tree?
>>>
>>
>> Unfortunately the microcode is required by the call to TempRamInit in
>> FSP in car_init, where the device tree functionality is not available.
>> We can of course duplicate one in device tree for reference, not sure
>> if it is necessary.
>
> OK I was hoping you weren't going to say that. There is not even a
> stack at this stage so device tree is out of the question. I wonder
> how common this is. Is there any way to provide a 'NULL'  microcode
> update and then do it later?

I tested this, by providing a 'NULL' microcode to FSP. However the FSP
TempRamInit() will just fail. So we may have to do it this way.

> This is some of the pain of dealing with binary blobs.
>
> Let's see where this lands but we may want to change things around in
> start.S to provide for this more nicely.
>
> Regards,
> Simon

Regards,
Bin
Pavel Machek Dec. 15, 2014, 10:34 p.m. UTC | #5 
On Thu 2014-12-04 23:02:46, Bin Meng wrote:
> Integrate the processor microcode version 1.05 for Tunnel Creek,
> CPUID device 20661h.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>  arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
>  1 file changed, 1288 insertions(+)
>  create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc
> 
> diff --git a/arch/x86/cpu/queensbay/M0220661105.inc b/arch/x86/cpu/queensbay/M0220661105.inc
> new file mode 100644
> index 0000000..f2b2b4e
> --- /dev/null
> +++ b/arch/x86/cpu/queensbay/M0220661105.inc
> @@ -0,0 +1,1288 @@
> +/*
> + * Copyright (C) 2013, Intel Corporation
> + *
> + * SPDX-License-Identifier:	Intel

Can we get the file under GPLv2+?

> + */
> +
> +/* External Header */

Comment here that this is processor microcode would be nice. And maybe
more self-describing filename?

Thanks,
									Pavel
Bin Meng Dec. 16, 2014, 2:28 a.m. UTC | #6 
Hi Pavel,

On Tue, Dec 16, 2014 at 6:34 AM, Pavel Machek <pavel@denx.de> wrote:
> On Thu 2014-12-04 23:02:46, Bin Meng wrote:
>> Integrate the processor microcode version 1.05 for Tunnel Creek,
>> CPUID device 20661h.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>  arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
>>  1 file changed, 1288 insertions(+)
>>  create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc
>>
>> diff --git a/arch/x86/cpu/queensbay/M0220661105.inc b/arch/x86/cpu/queensbay/M0220661105.inc
>> new file mode 100644
>> index 0000000..f2b2b4e
>> --- /dev/null
>> +++ b/arch/x86/cpu/queensbay/M0220661105.inc
>> @@ -0,0 +1,1288 @@
>> +/*
>> + * Copyright (C) 2013, Intel Corporation
>> + *
>> + * SPDX-License-Identifier:  Intel
>
> Can we get the file under GPLv2+?

I believe it is hard for Intel to release the microcode under GPLv2+ ...

>> + */
>> +
>> +/* External Header */
>
> Comment here that this is processor microcode would be nice. And maybe
> more self-describing filename?

The file name is extracted from Intel released microcode.dat. We
intend to use the same name to keep track of what version is used
here. Simon is working on patches to convert this to dtsi format, so
we can generate comments there from the microcode tool, Simon?

[snip]

Regards,
Bin
Simon Glass Dec. 16, 2014, 4:12 a.m. UTC | #7 
Hi Bin,

On 15 December 2014 at 19:28, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Pavel,
>
> On Tue, Dec 16, 2014 at 6:34 AM, Pavel Machek <pavel@denx.de> wrote:
>> On Thu 2014-12-04 23:02:46, Bin Meng wrote:
>>> Integrate the processor microcode version 1.05 for Tunnel Creek,
>>> CPUID device 20661h.
>>>
>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>> ---
>>>  arch/x86/cpu/queensbay/M0220661105.inc | 1288 ++++++++++++++++++++++++++++++++
>>>  1 file changed, 1288 insertions(+)
>>>  create mode 100644 arch/x86/cpu/queensbay/M0220661105.inc
>>>
>>> diff --git a/arch/x86/cpu/queensbay/M0220661105.inc b/arch/x86/cpu/queensbay/M0220661105.inc
>>> new file mode 100644
>>> index 0000000..f2b2b4e
>>> --- /dev/null
>>> +++ b/arch/x86/cpu/queensbay/M0220661105.inc
>>> @@ -0,0 +1,1288 @@
>>> +/*
>>> + * Copyright (C) 2013, Intel Corporation
>>> + *
>>> + * SPDX-License-Identifier:  Intel
>>
>> Can we get the file under GPLv2+?
>
> I believe it is hard for Intel to release the microcode under GPLv2+ ...
>
>>> + */
>>> +
>>> +/* External Header */
>>
>> Comment here that this is processor microcode would be nice. And maybe
>> more self-describing filename?
>
> The file name is extracted from Intel released microcode.dat. We
> intend to use the same name to keep track of what version is used
> here. Simon is working on patches to convert this to dtsi format, so
> we can generate comments there from the microcode tool, Simon?

Yes the tool generates comments.

Regards,
Simon
diff mbox

Patch

diff --git a/arch/x86/cpu/queensbay/M0220661105.inc b/arch/x86/cpu/queensbay/M0220661105.inc
new file mode 100644
index 0000000..f2b2b4e
--- /dev/null
+++ b/arch/x86/cpu/queensbay/M0220661105.inc
@@ -0,0 +1,1288 @@ 
+/*
+ * Copyright (C) 2013, Intel Corporation
+ *
+ * SPDX-License-Identifier:	Intel
+ */
+
+/* External Header */
+.long 0x00000001 /* Header Version */
+.long 0x00000105 /* Update Revision */
+.long 0x07182011 /* Date */
+.long 0x00020661 /* Processor Signature */
+.long 0x52558795 /* Checksum */
+.long 0x00000001 /* Loader Revision */
+.long 0x00000002 /* Processor Flags */
+.long 0x000013d0 /* Data Size (excluding headers) */
+.long 0x00001400 /* Total Size (including headers) */
+.long 0x00000000 /* Reserved */
+.long 0x00000000 /* Reserved */
+.long 0x00000000 /* Reserved */
+/* Data */
+.long 0x00000000
+.long 0x000000a1
+.long 0x00020001
+.long 0x00000105
+.long 0x00000019
+.long 0x00050100
+.long 0x20110715
+.long 0x00000401
+.long 0x00000001
+.long 0x00020661
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+.long 0x00000000
+.long 0x00000000
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+.long 0x0420b3fe
+.long 0xe8da74a1
+.long 0xfc7dda49
+.long 0x9010dba4
+.long 0x8b992a7d
+.long 0x9ba6ebb7
+.long 0x7148829b
+.long 0x1dbd5735
+.long 0x9b3da7d3
+.long 0x0b3125f2
+.long 0xf6fc1fad
+.long 0x5b075f2d
+.long 0xf4e62d59
+.long 0xf438e469
+.long 0xc4cad84e
+.long 0x7f949ca7
+.long 0x90955fb9
+.long 0xc9e5edb8
+.long 0x29921c0b
+.long 0x0eb3a485
+.long 0x20991465
+.long 0xa8613443
+.long 0x4fda6f18
+.long 0x9770eeba
+.long 0xbdc1cad3
+.long 0xa22cc38b
+.long 0x12154f91
+.long 0x7894619b
+.long 0xc9532a58
+.long 0x004a624e
+.long 0xec45e477
+.long 0x5931826f
+.long 0x6b76c4a9
+.long 0x28add60d
+.long 0xc5adbdfa
+.long 0x95fd4b70
+.long 0x56506408
+.long 0x219893e1
+.long 0x620b6576
+.long 0x1a947688
+.long 0x9f2312f8
+.long 0x13ce6928
+.long 0xc792d2a4
+.long 0xfd40baec
+.long 0x8ffdd283
+.long 0xc0cc45dd
+.long 0xcbb7127c
+.long 0xbb200adc
+.long 0x4de39b0d
+.long 0x9d6ad14d
+.long 0x46548325
+.long 0x218c4db9
+.long 0x1080ca97
+.long 0x2493d0dd
+.long 0x1fe3ff95
+.long 0xc93661a8
+.long 0x71c58a82
+.long 0x00fca79a
+.long 0x8cc42c38
+.long 0x86715f01
+.long 0x0d04fdc3
+.long 0xe0085450
+.long 0x4cc3cd21
+.long 0x596026bd
+.long 0x3e672f6e
+.long 0x1b3c52e4
+.long 0xb36ba53b
+.long 0x3839341c
+.long 0x54dfc0ab
+.long 0xe8f1a48b
+.long 0x92c5d4fb
+.long 0x84c878b6
+.long 0xf1e23bff
+.long 0x703501ca
+.long 0xdf9805fb
+.long 0x1dccb93c
+.long 0xa38cbae3
+.long 0xeeecd7c3
+.long 0x0b4ae80a
+.long 0xc3f0700d
+.long 0xff103196