From patchwork Tue Nov 11 01:00:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 409148 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 15E5414011B for ; Tue, 11 Nov 2014 12:04:28 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B358F4B6FE; Tue, 11 Nov 2014 02:03:46 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZDL9SIneN9Rf; Tue, 11 Nov 2014 02:03:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 422434B7AC; Tue, 11 Nov 2014 02:02:36 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D05644B713 for ; Tue, 11 Nov 2014 02:01:22 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id NjFoQWdLLHEa for ; Tue, 11 Nov 2014 02:01:22 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f73.google.com (mail-pa0-f73.google.com [209.85.220.73]) by theia.denx.de (Postfix) with ESMTPS id 9420A4B704 for ; Tue, 11 Nov 2014 02:01:18 +0100 (CET) Received: by mail-pa0-f73.google.com with SMTP id lj1so1442629pab.4 for ; Mon, 10 Nov 2014 17:01:17 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jhs2kSApOBSXX3KkgVftUb8LFWenaEt0vRxParzuEpE=; b=m0L+zAicPzX3QjYJl4ehC4ktyHmGOcdkGjxN2ALNsYbAnXDGwTtI3PCSw/Sd8azzg6 fFcDOKMmES0wix7uxSBO5WK9GHUZn+7pSiUyOh2fD6AO03a1Dmls8cpl+ww3oa0Noi1A BjfHYxlxNK7GegpKOg8DKb7017W28f2h3gFiEJUxFjdp+48+uXm3JXOZi+9MrrsNczPR koQAuHuBsdeQKR5Ygdy9kdULqImXLec4vxvKVWPI/2xkhPRVa28X8ORsUANJKsupkFwL r5TLDxc4Iqc63JdL3+2y5oMFB3OZWgWh4zUTZ3e1Lh+vWJPDZRmfyYGiCJ0ZuZwtbMsf /IEA== X-Gm-Message-State: ALoCoQl71jH7S+00AaYvb7ts8jji3g3KzpjVjWMA/bwzL5m0SYDtMB8FRkJI+dF49hxrYyYnx2wl X-Received: by 10.67.30.169 with SMTP id kf9mr28032000pad.28.1415667677126; Mon, 10 Nov 2014 17:01:17 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id s23si751018yhf.0.2014.11.10.17.01.16 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Nov 2014 17:01:17 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id ZHoplK0j.4; Mon, 10 Nov 2014 17:01:16 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 23E6E221207; Mon, 10 Nov 2014 18:01:16 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 10 Nov 2014 18:00:46 -0700 Message-Id: <1415667650-14899-30-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1415667650-14899-1-git-send-email-sjg@chromium.org> References: <1415667650-14899-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH v2 29/33] x86: chromebook_link: Enable GPIO support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enable GPIO support and provide the required GPIO setup information to the driver. Signed-off-by: Simon Glass --- Changes in v2: None arch/x86/dts/link.dts | 3 + board/google/chromebook_link/link.c | 107 ++++++++++++++++++++++++++++++++++++ include/configs/chromebook_link.h | 4 +- 3 files changed, 111 insertions(+), 3 deletions(-) diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts index f1b7bf0..74b2198 100644 --- a/arch/x86/dts/link.dts +++ b/arch/x86/dts/link.dts @@ -14,18 +14,21 @@ gpioa { compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; reg = <0 0x10>; bank-name = "A"; }; gpiob { compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; reg = <0x30 0x10>; bank-name = "B"; }; gpioc { compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; reg = <0x40 0x10>; bank-name = "C"; }; diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index ffa9d60..88cee05 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -5,6 +5,7 @@ */ #include +#include int arch_early_init_r(void) { @@ -15,3 +16,109 @@ int board_early_init_r(void) { return 0; } + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ + .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ + .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ + .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ + .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ + .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ + .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ + .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ + .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ + .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ + .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio36 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_map link_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +int board_early_init_f(void) +{ + ich_gpio_set_gpio_map(&link_gpio_map); + + return 0; +} diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 0b8c067..3063bd9 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -19,6 +19,7 @@ #define CONFIG_SYS_CAR_SIZE (128 * 1024) #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_SYS_X86_START16 0xfffff800 +#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_X86_RESET_VECTOR @@ -40,9 +41,6 @@ * follow-on patches in this series. Add undefs here to avoid every patch * having to put things back into x86-common.h */ -#undef CONFIG_INTEL_ICH6_GPIO -#undef CONFIG_DM_GPIO -#undef CONFIG_CMD_GPIO #undef CONFIG_VIDEO #undef CONFIG_CFB_CONSOLE #undef CONFIG_ICH_SPI