From patchwork Tue Nov 11 01:00:32 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 409139 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 71C8214011B for ; Tue, 11 Nov 2014 12:03:12 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A07254B823; Tue, 11 Nov 2014 02:02:55 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id f+D91bRL9R4U; Tue, 11 Nov 2014 02:02:55 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EBFAC4B779; Tue, 11 Nov 2014 02:01:57 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 796524B6F5 for ; Tue, 11 Nov 2014 02:01:21 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 75lPg8I1PqFw for ; Tue, 11 Nov 2014 02:01:21 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ig0-f202.google.com (mail-ig0-f202.google.com [209.85.213.202]) by theia.denx.de (Postfix) with ESMTPS id 49EDA4B716 for ; Tue, 11 Nov 2014 02:01:16 +0100 (CET) Received: by mail-ig0-f202.google.com with SMTP id r10so24621igi.3 for ; Mon, 10 Nov 2014 17:01:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-type:content-transfer-encoding; bh=YhP+V3sq62Aap+oegndBs6VWVIrkXfYallWwSUEfOcY=; b=OPUp6zmUkY7GRrD7quC7vtzfhmtMBqjKxAxnyIGAhn/KN4EeUHW/8MPWYYXgcv/ujG XxnHHy+A9pLB0DIc+VWrEZdxDzJh4f4RTRAElnpu0vQWfFaWaXV4xIyAuM19a+RAYd78 HEQZhpqv98V91ZvAkJdJGYTWNOpq/waIgwIiZdfQKV8+w5nnl0mIAzaG62mDmG6HnNSG XwHipP/aE7o4iJ7KJA7iS5MoHqbub999sWzjUIkTCoqPGC18gLvS2Nwp2NTiBedwmtHh Y0c7QVhA52G5Pe2R6xDb/AnowMarcH57O/jtQQ3kJylL9K6PISGV+hgZD3zhrLeqPFHv Jb8g== X-Gm-Message-State: ALoCoQmImRnsrotv4guvbmxTliA6vDotjhuKusKkbP5qp3Qt3QdDTgr9L/vAWQKPXiSuEo/4Mxx8 X-Received: by 10.182.98.232 with SMTP id el8mr28752732obb.42.1415667675767; Mon, 10 Nov 2014 17:01:15 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id k66si746161yho.7.2014.11.10.17.01.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 10 Nov 2014 17:01:15 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id QIf9cFaS.2; Mon, 10 Nov 2014 17:01:15 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id BC1E122120C; Mon, 10 Nov 2014 18:01:14 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Mon, 10 Nov 2014 18:00:32 -0700 Message-Id: <1415667650-14899-16-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1415667650-14899-1-git-send-email-sjg@chromium.org> References: <1415667650-14899-1-git-send-email-sjg@chromium.org> MIME-Version: 1.0 Cc: Graeme Russ Subject: [U-Boot] [PATCH v2 15/33] x86: Refactor PCI to permit alternate init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de We want access PCI earlier in the init sequence, so refactor the code so that it does not require use of a BSS variable to work. This will allow us to use early malloc() to store information about a PCI hose. Common PCI code moves to arch/x86/cpu/pci.c and a new board_pci_setup_hose() function is provided by boards to set up the (single) hose used by that board. Signed-off-by: Simon Glass --- Changes in v2: None arch/x86/cpu/Makefile | 1 + arch/x86/cpu/coreboot/pci.c | 22 ++++++++-------------- arch/x86/cpu/pci.c | 26 ++++++++++++++++++++++++++ arch/x86/include/asm/pci.h | 11 +++++++++++ 4 files changed, 46 insertions(+), 14 deletions(-) create mode 100644 arch/x86/cpu/pci.c diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 9d38ef7..97f36d5 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -11,3 +11,4 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o call64.o +obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 33f16a3..130fd88 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -13,8 +13,6 @@ #include #include -static struct pci_controller coreboot_hose; - static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) { @@ -31,19 +29,15 @@ static struct pci_config_table pci_coreboot_config_table[] = { {} }; -void pci_init_board(void) +void board_pci_setup_hose(struct pci_controller *hose) { - coreboot_hose.config_table = pci_coreboot_config_table; - coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0; - - pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, - PCI_REGION_MEM); - coreboot_hose.region_count = 1; - - pci_setup_type1(&coreboot_hose); + hose->config_table = pci_coreboot_config_table; + hose->first_busno = 0; + hose->last_busno = 0; - pci_register_hose(&coreboot_hose); + pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + hose->region_count = 1; - pci_hose_scan(&coreboot_hose); + pci_setup_type1(hose); } diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c new file mode 100644 index 0000000..030cbbc --- /dev/null +++ b/arch/x86/cpu/pci.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008,2009 + * Graeme Russ, + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static struct pci_controller x86_hose; + +void pci_init_board(void) +{ + struct pci_controller *hose = &x86_hose; + + board_pci_setup_hose(hose); + pci_register_hose(hose); + + pci_hose_scan(hose); +} diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 6b16188..c160707 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -12,5 +12,16 @@ #define DEFINE_PCI_DEVICE_TABLE(_table) \ const struct pci_device_id _table[] +struct pci_controller; + void pci_setup_type1(struct pci_controller *hose); + +/** + * board_pci_setup_hose() - Set up the PCI hose + * + * This is called by the common x86 PCI code to set up the PCI controller + * hose. It may be called when no memory/BSS is available so should just + * store things in 'hose' and not in BSS variables. + */ +void board_pci_setup_hose(struct pci_controller *hose); #endif