From patchwork Fri Nov 7 12:50:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 408099 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 040ED1400A8 for ; Fri, 7 Nov 2014 23:51:42 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8AFE54B9DD; Fri, 7 Nov 2014 13:51:19 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Bep++sfGZ0oo; Fri, 7 Nov 2014 13:51:19 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D19CC4BA5A; Fri, 7 Nov 2014 13:51:00 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A1A7D4B955 for ; Fri, 7 Nov 2014 13:50:47 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fTV4Blg6P3Wy for ; Fri, 7 Nov 2014 13:50:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo4-p05-ob.smtp.rzone.de (mo4-p05-ob.smtp.rzone.de [81.169.146.182]) by theia.denx.de (Postfix) with ESMTPS id 71EAB4B953 for ; Fri, 7 Nov 2014 13:50:43 +0100 (CET) X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohfvxEndrDXKjzPMsB3oimjD61I4fPQhgcxW13 X-RZG-CLASS-ID: mo05 Received: from stefan-work.domain_not_set.invalid (b9168f14.cgn.dg-w.de [185.22.143.20]) by post.strato.de (RZmta 35.10 AUTH) with ESMTPA id g00baeqA7CoZVB8; Fri, 7 Nov 2014 13:50:35 +0100 (CET) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 7 Nov 2014 13:50:30 +0100 Message-Id: <1415364634-8290-3-git-send-email-sr@denx.de> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1415364634-8290-1-git-send-email-sr@denx.de> References: <1415364634-8290-1-git-send-email-sr@denx.de> Cc: Vince Bridgers , Marek Vasut , Dinh Nguyen , Chin Liang See , Pavel Machek Subject: [U-Boot] [PATCH 2/6] arm: socfpga: Add socfpga_spim_enable() to reset_manager.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller. This function is called from arch_early_init_r() if the SPI driver is enabled. Signed-off-by: Stefan Roese Cc: Chin Liang See Cc: Dinh Nguyen Cc: Vince Bridgers Cc: Marek Vasut Cc: Pavel Machek --- arch/arm/cpu/armv7/socfpga/misc.c | 6 ++++++ arch/arm/cpu/armv7/socfpga/reset_manager.c | 9 +++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 3 +++ 3 files changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 8c3e5f7..73cffd3 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -202,6 +202,12 @@ int arch_early_init_r(void) /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); + +#ifdef CONFIG_DESIGNWARE_SPI + /* Get Designware SPI controller out of reset */ + socfpga_spim_enable(); +#endif + return 0; } diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 1d3a95d..af9db85 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -104,3 +104,12 @@ void socfpga_emac_reset(int enable) #endif } } + +/* SPI Master enable (its held in reset by the preloader) */ +void socfpga_spim_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB); + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB); +} diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 1857b80..034135b 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -14,6 +14,7 @@ void socfpga_bridges_reset(int enable); void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void); +void socfpga_spim_enable(void); struct socfpga_reset_manager { u32 status; @@ -35,5 +36,7 @@ struct socfpga_reset_manager { #define RSTMGR_PERMODRST_EMAC0_LSB 0 #define RSTMGR_PERMODRST_EMAC1_LSB 1 #define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_SPIM0_LSB 18 +#define RSTMGR_PERMODRST_SPIM1_LSB 19 #endif /* _RESET_MANAGER_H_ */