From patchwork Fri Nov 7 01:08:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 407930 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2A9FA1400A0 for ; Fri, 7 Nov 2014 12:08:13 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 29D834BAB0; Fri, 7 Nov 2014 02:07:59 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jgG9dVJXoCqL; Fri, 7 Nov 2014 02:07:58 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 03E7E4BAAB; Fri, 7 Nov 2014 02:07:55 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9959B4BAA1 for ; Fri, 7 Nov 2014 02:07:49 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GO2eUyQEryw9 for ; Fri, 7 Nov 2014 02:07:49 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2on0148.outbound.protection.outlook.com [207.46.100.148]) by theia.denx.de (Postfix) with ESMTPS id 2F5A34BA80 for ; Fri, 7 Nov 2014 02:07:42 +0100 (CET) Received: from CH1PR03CA003.namprd03.prod.outlook.com (10.255.156.148) by BL2PR03MB244.namprd03.prod.outlook.com (10.255.231.26) with Microsoft SMTP Server (TLS) id 15.1.11.14; Fri, 7 Nov 2014 01:07:38 +0000 Received: from BN1AFFO11FD022.protection.gbl (10.255.156.132) by CH1PR03CA003.outlook.office365.com (10.255.156.148) with Microsoft SMTP Server (TLS) id 15.1.16.15 via Frontend Transport; Fri, 7 Nov 2014 01:07:38 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD022.mail.protection.outlook.com (10.58.52.82) with Microsoft SMTP Server (TLS) id 15.1.6.13 via Frontend Transport; Fri, 7 Nov 2014 01:07:38 +0000 Received: from linux-vaa1.ap.freescale.net (linux-vaa1.ap.freescale.net [10.193.102.217]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id sA717P9N023109; Thu, 6 Nov 2014 18:07:35 -0700 From: Peng Fan To: Date: Fri, 7 Nov 2014 09:08:14 +0800 Message-ID: <1415322494-20415-4-git-send-email-Peng.Fan@freescale.com> X-Mailer: git-send-email 1.8.4.5 In-Reply-To: <1415322494-20415-1-git-send-email-Peng.Fan@freescale.com> References: <1415322494-20415-1-git-send-email-Peng.Fan@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(189002)(199003)(107046002)(2351001)(106466001)(229853001)(62966003)(77156002)(104166001)(50226001)(50986999)(6806004)(4396001)(88136002)(102836001)(31966008)(89996001)(105606002)(95666004)(21056001)(84676001)(76176999)(87936001)(92726001)(92566001)(110136001)(97736003)(104016003)(48376002)(36756003)(50466002)(46102003)(44976005)(19580405001)(68736004)(19580395003)(87286001)(99396003)(64706001)(86362001)(120916001)(575784001)(20776003)(47776003); DIR:OUT; SFP:1102; SCL:1; SRVR:BL2PR03MB244; H:tx30smr01.am.freescale.net; FPR:; MLV:sfv; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB244; X-Exchange-Antispam-Report-Test: UriScan:; X-Forefront-PRVS: 03883BD916 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Peng.Fan@freescale.com; X-OriginatorOrg: freescale.com Cc: marex@denx.de, fabio.estevam@freescale.com, u-boot@lists.denx.de, B37916@freescale.com Subject: [U-Boot] [PATCH v3 3/3] imx:mx6slevk add board level support for usb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode There are two usb port on mx6slevk board: 1. otg port 2. host port The following are the connection between usb controller and board usb interface, host port has not ID pin set: otg1 core <---> board otg port otg2 core <---> board host port In order to make host port work, board_usb_phy_mode return 0 to let ehci-mx6.c driver decide otg2 core to works in host mode. Signed-off-by: Peng Fan Signed-off-by: Ye Li --- Changes v3: implement board_usb_phy_mode Changes v2: Add otg polarity setting move pinmux into board_init set pinmux setting static arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 +++ board/freescale/mx6slevk/mx6slevk.c | 63 ++++++++++++++++++++++++++++++ include/configs/mx6slevk.h | 14 +++++++ 3 files changed, 82 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 045ccc4..17b4798 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -34,5 +34,10 @@ enum { MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0), MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index a500133..e9ec77e 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -150,6 +151,63 @@ static int setup_fec(void) } #endif +#ifdef CONFIG_USB_EHCI_MX6 +#define USB_OTHERREGS_OFFSET 0x800 +#define USBPHY_CTRL 0x30 +#define UCTRL_PWR_POL (1 << 9) +#define USBPHY_CTRL_OTG_ID 0x08000000 + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OTG1 */ + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + void __iomem *phy_reg; + void __iomem *phy_ctrl; + u32 val; + + switch (port) { + case 0: + phy_reg = (void __iomem *)USB_PHY0_BASE_ADDR; + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + val = __raw_readl(phy_ctrl); + return val & USBPHY_CTRL_OTG_ID; + case 1: + /* Work in HOST mode. */ + return 0; + } + + /* suppress warning msg */ + return 0; +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif int board_early_init_f(void) { @@ -168,6 +226,11 @@ int board_init(void) #ifdef CONFIG_FEC_MXC setup_fec(); #endif + +#ifdef CONFIG_USB_EHCI_MX6 + setup_usb(); +#endif + return 0; } diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index fddedf1..021dc0e 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -210,4 +210,18 @@ #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #endif +/* USB Configs */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + #endif /* __CONFIG_H */