From patchwork Thu Nov 6 20:20:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 407680 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 82C3814007D for ; Fri, 7 Nov 2014 07:21:38 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ECA724BBDF; Thu, 6 Nov 2014 21:21:36 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id m7VAP5Luns8w; Thu, 6 Nov 2014 21:21:36 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 38A174BBEB; Thu, 6 Nov 2014 21:21:32 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5516B4BA4D for ; Thu, 6 Nov 2014 21:21:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lbOB0HJqSmvc for ; Thu, 6 Nov 2014 21:21:26 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f74.google.com (mail-pa0-f74.google.com [209.85.220.74]) by theia.denx.de (Postfix) with ESMTPS id E8CA04BA41 for ; Thu, 6 Nov 2014 21:21:25 +0100 (CET) Received: by mail-pa0-f74.google.com with SMTP id kx10so314294pab.5 for ; Thu, 06 Nov 2014 12:21:24 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dYLdlGgQHEQMV1tmiVP6oDMMrE6Bj2NGazB95Tf8yHY=; b=QfTMAroHMTL8x2aWaj2GKSNB2kyY3Cx2vhG7KhnWAkGcz1Nj5h+Bgn43Yhu6XYqz45 +tC2E5RNl/9z/2dIypdGHg07R4GR4M44ekVYw/MKSUfRpen3Uw3pXiheRgpd0ZxWhBYu 8k7eH9OP97Z/QuRCM2JA9BFJvVWC8DhMA0skUbxLSRaB1mLeCTCFh0dbVZX/tPsH6ymq tXW8wZBs4m+mVa3bzPAkJSOS06+fpX+ijYxgkurclL7Qt+ikwU531UOs5I/nGd4DdTHK 2wyT/4e8RoLYQryEIWQCzCTg+GHpxtmCQ6nFA8edeUlXbhDuR8zJUDKPBJ36iIVSHd8w vppQ== X-Gm-Message-State: ALoCoQnrBRpN2f4UArV137VgnsKuVNP9DPyFjYxtejtR3lJf81K0z/oyKtMHlOggz3sMkh568P0t X-Received: by 10.66.119.41 with SMTP id kr9mr5222971pab.24.1415305283989; Thu, 06 Nov 2014 12:21:23 -0800 (PST) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id s23si273513yhf.0.2014.11.06.12.21.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Nov 2014 12:21:23 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id fLrkph1w.3; Thu, 06 Nov 2014 12:21:23 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 71100220E74; Thu, 6 Nov 2014 13:21:23 -0700 (MST) From: Simon Glass To: U-Boot Mailing List Date: Thu, 6 Nov 2014 13:20:14 -0700 Message-Id: <1415305231-30180-23-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1415305231-30180-1-git-send-email-sjg@chromium.org> References: <1415305231-30180-1-git-send-email-sjg@chromium.org> Cc: Graeme Russ Subject: [U-Boot] [PATCH 22/39] x86: Move Coreboot PCI into common cpu area X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This code is not really Coreboot-specific, so move it into the common area and rename it. Signed-off-by: Simon Glass --- arch/x86/cpu/Makefile | 1 + arch/x86/cpu/coreboot/Makefile | 1 - arch/x86/cpu/{coreboot => }/pci.c | 24 +++++++++++++----------- 3 files changed, 14 insertions(+), 12 deletions(-) rename arch/x86/cpu/{coreboot => }/pci.c (63%) diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 9d38ef7..97f36d5 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -11,3 +11,4 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o call64.o +obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile index cd0bf4e..65cf2cb 100644 --- a/arch/x86/cpu/coreboot/Makefile +++ b/arch/x86/cpu/coreboot/Makefile @@ -19,4 +19,3 @@ obj-$(CONFIG_SYS_COREBOOT) += tables.o obj-$(CONFIG_SYS_COREBOOT) += ipchecksum.o obj-$(CONFIG_SYS_COREBOOT) += sdram.o obj-$(CONFIG_SYS_COREBOOT) += timestamp.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/pci.c similarity index 63% rename from arch/x86/cpu/coreboot/pci.c rename to arch/x86/cpu/pci.c index 33f16a3..f35c8b3 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/pci.c @@ -13,7 +13,7 @@ #include #include -static struct pci_controller coreboot_hose; +static struct pci_controller x86_hose; static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *table) @@ -24,7 +24,7 @@ static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, pci_hose_scan_bus(hose, secondary); } -static struct pci_config_table pci_coreboot_config_table[] = { +static struct pci_config_table pci_x86_config_table[] = { /* vendor, device, class, bus, dev, func */ { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, @@ -33,17 +33,19 @@ static struct pci_config_table pci_coreboot_config_table[] = { void pci_init_board(void) { - coreboot_hose.config_table = pci_coreboot_config_table; - coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0; + struct pci_controller *hose = &x86_hose; - pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, - PCI_REGION_MEM); - coreboot_hose.region_count = 1; + hose->config_table = pci_x86_config_table; + hose->first_busno = 0; + hose->last_busno = 0; - pci_setup_type1(&coreboot_hose); + pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + hose->region_count = 1; - pci_register_hose(&coreboot_hose); + pci_setup_type1(hose); - pci_hose_scan(&coreboot_hose); + pci_register_hose(hose); + + pci_hose_scan(hose); }