From patchwork Wed Nov 5 15:38:06 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 407050 X-Patchwork-Delegate: ijc@hellion.org.uk Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2E88914003E for ; Thu, 6 Nov 2014 02:39:27 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B86A04BE7D; Wed, 5 Nov 2014 16:39:00 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id K1LBZP2uvtHu; Wed, 5 Nov 2014 16:39:00 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B4B844BE48; Wed, 5 Nov 2014 16:38:48 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4A6BD4BE20 for ; Wed, 5 Nov 2014 16:38:42 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ceHoLzQUnqg7 for ; Wed, 5 Nov 2014 16:38:42 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by theia.denx.de (Postfix) with ESMTPS id D20604BC36 for ; Wed, 5 Nov 2014 16:38:34 +0100 (CET) Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id sA5FcL0Y028701 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 5 Nov 2014 10:38:22 -0500 Received: from shalem.localdomain.com (vpn1-7-222.ams2.redhat.com [10.36.7.222]) by int-mx09.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id sA5Fc9hP003999; Wed, 5 Nov 2014 10:38:20 -0500 From: Hans de Goede To: Ian Campbell Date: Wed, 5 Nov 2014 16:38:06 +0100 Message-Id: <1415201888-6194-8-git-send-email-hdegoede@redhat.com> In-Reply-To: <1415201888-6194-1-git-send-email-hdegoede@redhat.com> References: <1415201888-6194-1-git-send-email-hdegoede@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.22 Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [U-Boot] [PATCH v2 7/9] sun6i: Poke magic sram controller register to avoid cache issues X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Without this the cache will only work in write-through mode, and as soon as it is put in write-back mode things break. Signed-off-by: Hans de Goede --- arch/arm/cpu/armv7/sunxi/board.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 6c812fc..9b3e80c 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -114,6 +114,11 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { +#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I + /* Magic (undocmented) value taken from boot0, without this DRAM + * access gets messed up (seems cache related) */ + setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); +#endif #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \ defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */