From patchwork Thu Oct 23 19:16:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 402636 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id EAC2414003E for ; Fri, 24 Oct 2014 06:22:38 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 47B32A7756; Thu, 23 Oct 2014 21:22:34 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pROsKtSJtTDQ; Thu, 23 Oct 2014 21:22:34 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CD534A772D; Thu, 23 Oct 2014 21:22:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BB388A768D for ; Thu, 23 Oct 2014 21:22:24 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id msZowVX+yeHw for ; Thu, 23 Oct 2014 21:22:24 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f202.google.com (mail-pd0-f202.google.com [209.85.192.202]) by theia.denx.de (Postfix) with ESMTPS id 4A4B8A7543 for ; Thu, 23 Oct 2014 21:22:20 +0200 (CEST) Received: by mail-pd0-f202.google.com with SMTP id fp1so8732pdb.5 for ; Thu, 23 Oct 2014 12:22:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t7+giqZfj+5s+XlVxk/HPGMVlZFt4Rh87hKKYn3V038=; b=J8xCvAJ5E62RI5X9+CobyiBVglPRqzThK+MAGsVifQJ6xTAXk8qK5XX6SoyGMFeAuC BWjwRhESfQk8GKwv0faEV3UNH39bKf2LhJsTn834/r4hwNcqYRpfc9i6JHHGurBdwmRW TodYBPPNAMA70jsJLvf50NiFLAi6i2opF5W9iWOTePHPKYNYOWoWDHi8Z4XKgGFwOVV5 HnDDeYSjlQWBHJ0Mz5Y+FfH4q6Syx828olxJ1NpSHjJjlF4DyIVp76M3J35wFUi4uZaq 8dYPqgu5Bf13/dveHI2qxyM7to24sXpOlxw/DKIKbiDxK7r+5KgVahkC8+qLe7VppRuS s2zg== X-Gm-Message-State: ALoCoQl+cSUpXADLTsmMGgtzmPa+nIxWZm3NrKbT9/g2m3NMs5b279g4O1Lppf4YIaNoFIIM6rW8 X-Received: by 10.67.5.33 with SMTP id cj1mr4293303pad.39.1414092139157; Thu, 23 Oct 2014 12:22:19 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id t28si142658yhb.4.2014.10.23.12.22.18 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Oct 2014 12:22:19 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id bCeB75Zm.1; Thu, 23 Oct 2014 12:22:18 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 9CF0E220A6A; Thu, 23 Oct 2014 13:17:14 -0600 (MDT) From: Simon Glass To: u-boot@lists.denx.de Date: Thu, 23 Oct 2014 13:16:09 -0600 Message-Id: <1414091770-26319-13-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1414091770-26319-1-git-send-email-sjg@chromium.org> References: <1414091770-26319-1-git-send-email-sjg@chromium.org> Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH v2 12/13] dm: tegra: Enable driver model in SPL and adjust the GPIO driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Use the full driver model GPIO and serial drivers in SPL now that these are supported. Since device tree is not available they will use platform data. Remove the special SPL GPIO function as it is no longer needed. This is all in one commit to maintain bisectability. Signed-off-by: Simon Glass --- Changes in v2: - Rebase on top of the SPI series board/nvidia/seaboard/seaboard.c | 4 +--- drivers/gpio/Makefile | 4 ++++ drivers/gpio/tegra_gpio.c | 27 +++++++++++---------------- include/configs/tegra-common.h | 12 +++--------- 4 files changed, 19 insertions(+), 28 deletions(-) diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 6a243f0..3e52826 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -19,10 +19,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ -#ifndef CONFIG_SPL_BUILD gpio_request(GPIO_PI3, NULL); -#endif - tegra_spl_gpio_direction_output(GPIO_PI3, 0); + gpio_direction_output(GPIO_PI3, 0); } #endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index aa11f15..fe9a3b2 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -8,6 +8,10 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_DM_GPIO) += gpio-uclass.o endif +/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */ +ifdef CONFIG_TEGRA_GPIO +obj-$(CONFIG_DM_GPIO) += gpio-uclass.o +endif obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 88f7ef5..a1e51c0 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -131,21 +131,6 @@ static void set_level(unsigned gpio, int high) writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); } -/* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int tegra_spl_gpio_direction_output(int gpio, int value) -{ - /* Configure as a GPIO */ - set_config(gpio, 1); - - /* Configure GPIO output value. */ - set_level(gpio, value); - - /* Configure GPIO direction as output. */ - set_direction(gpio, 1); - - return 0; -} - /* * Generic_GPIO primitives. */ @@ -320,12 +305,19 @@ static int gpio_tegra_bind(struct udevice *parent) int bank_count; int bank; int ret; - int len; /* If this is a child device, there is nothing to do here */ if (plat) return 0; + /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ +#ifdef CONFIG_SPL_BUILD + ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + bank_count = TEGRA_GPIO_BANKS; +#else + { + int len; + /* * This driver does not make use of interrupts, other than to figure * out the number of GPIO banks @@ -335,6 +327,8 @@ static int gpio_tegra_bind(struct udevice *parent) bank_count = len / 3 / sizeof(u32); ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, parent->of_offset, "reg"); + } +#endif for (bank = 0; bank < bank_count; bank++) { int port; @@ -370,4 +364,5 @@ U_BOOT_DRIVER(gpio_tegra) = { .probe = gpio_tegra_probe, .priv_auto_alloc_size = sizeof(struct tegra_port_info), .ops = &gpio_tegra_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 4719ee1..b72f64f 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -19,13 +19,12 @@ #include /* get chip and board defs */ #define CONFIG_DM +#define CONFIG_SPL_DM #define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#ifndef CONFIG_SPL_BUILD #define CONFIG_DM_SERIAL -#endif #define CONFIG_DM_SPI #define CONFIG_DM_SPI_FLASH +#define CONFIG_DM_GPIO #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE @@ -51,13 +50,7 @@ /* * NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#else #define CONFIG_TEGRA_SERIAL -#endif #define CONFIG_SYS_NS16550 /* @@ -137,6 +130,7 @@ GENERATED_GBL_DATA_SIZE) #define CONFIG_TEGRA_GPIO + #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM