From patchwork Sat Oct 11 06:40:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiqiang Hou X-Patchwork-Id: 398818 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 1655114012E for ; Sat, 11 Oct 2014 18:14:18 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EFC35A7584; Sat, 11 Oct 2014 09:14:14 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rxGybT6aU+k6; Sat, 11 Oct 2014 09:14:14 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1BA2EA7586; Sat, 11 Oct 2014 09:14:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E428AA7586 for ; Sat, 11 Oct 2014 09:14:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WNl8Z5wxea3W for ; Sat, 11 Oct 2014 09:14:08 +0200 (CEST) X-Greylist: delayed 1978 seconds by postgrey-1.32 at theia; Sat, 11 Oct 2014 09:14:05 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2on0103.outbound.protection.outlook.com [65.55.169.103]) by theia.denx.de (Postfix) with ESMTPS id 78E6AA7584 for ; Sat, 11 Oct 2014 09:14:05 +0200 (CEST) Received: from BN3PR0301CA0040.namprd03.prod.outlook.com (25.160.180.178) by BL2PR03MB500.namprd03.prod.outlook.com (10.141.93.152) with Microsoft SMTP Server (TLS) id 15.0.1049.19; Sat, 11 Oct 2014 06:41:05 +0000 Received: from BN1AFFO11FD037.protection.gbl (2a01:111:f400:7c10::150) by BN3PR0301CA0040.outlook.office365.com (2a01:111:e400:4000::50) with Microsoft SMTP Server (TLS) id 15.0.1049.19 via Frontend Transport; Sat, 11 Oct 2014 06:41:04 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD037.mail.protection.outlook.com (10.58.52.241) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Sat, 11 Oct 2014 06:41:04 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s9B6exjr008298; Fri, 10 Oct 2014 23:41:00 -0700 From: Hou Zhiqiang To: Date: Sat, 11 Oct 2014 14:40:29 +0800 Message-ID: <1413009629-29995-1-git-send-email-B48286@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(189002)(199003)(20776003)(97736003)(47776003)(88136002)(64706001)(104166001)(102836001)(105606002)(85852003)(89996001)(62966002)(2351001)(229853001)(107046002)(80022003)(46102003)(21056001)(48376002)(99396003)(81156004)(106466001)(120916001)(50466002)(76482002)(69596002)(36756003)(104016003)(68736004)(19580395003)(19580405001)(6806004)(44976005)(110136001)(85306004)(84676001)(77156001)(26826002)(4396001)(87936001)(50986999)(92566001)(87286001)(92726001)(50226001)(93916002)(95666004)(86362001)(31966008); DIR:OUT; SFP:1102; SCL:1; SRVR:BL2PR03MB500; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB500; X-Forefront-PRVS: 0361212EA8 Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=B48286@freescale.com; X-OriginatorOrg: freescale.com Cc: B21284@freescale.com, Hou Zhiqiang Subject: [U-Boot] [PATCH V2] sf: Add support for flag status register on Micron chips X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Enter 3 Byte address mode at first, because it may change to 4 Byte address mode in kernel driver and not reset to 3 Byte address mode after reboot. Add clear flag status register operation that some Micron SPI flash chips required after reading the flag status register to check some operations completion. Signed-off-by: Hou Zhiqiang Signed-off-by: Mingkai.Hu --- V1: Based on git://git.denx.de/u-boot.git. Also can be applied to git://www.denx.de/git/u-boot-mpc85xx.git. Tested on board T2080QDS and T2080RDB. V2: Add the operation of enter 3 Byte address mode in probe. drivers/mtd/spi/sf_internal.h | 17 ++++++++++++ drivers/mtd/spi/sf_ops.c | 64 +++++++++++++++++++++++++++++++++++++------ drivers/mtd/spi/sf_probe.c | 5 ++++ 3 files changed, 78 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 19d4914..49e5a2c 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -36,6 +36,11 @@ #define CMD_WRITE_ENABLE 0x06 #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#define CMD_CLEAR_FLAG_STATUS 0x50 + +/* Used for Macronix and Winbond flashes */ +#define CMD_ENTER_4B_ADDR 0xB7 +#define CMD_EXIT_4B_ADDR 0xE9 /* Read commands */ #define CMD_READ_ARRAY_SLOW 0x03 @@ -59,6 +64,8 @@ #define STATUS_QEB_WINSPAN (1 << 1) #define STATUS_QEB_MXIC (1 << 6) #define STATUS_PEC (1 << 7) +#define STATUS_PROT (1 << 1) +#define STATUS_ERASE (1 << 5) #ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN #define STATUS_SRWD (1 << 7) /* SR write protect */ @@ -124,6 +131,12 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); } +/* Clear flag status register */ +static inline int spi_flash_cmd_clear_flag_status(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_CLEAR_FLAG_STATUS, NULL, 0); +} + /* * Send the read status command to the device and wait for the wip * (write-in-progress) bit to clear itself. @@ -160,4 +173,8 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, size_t len, void *data); +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable); +#endif + #endif /* _SF_INTERNAL_H_ */ diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c index 85cf22d..8a532b8 100644 --- a/drivers/mtd/spi/sf_ops.c +++ b/drivers/mtd/spi/sf_ops.c @@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc) } #endif +#if defined(CONFIG_SPI_FLASH_STMICRO) +int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable) +{ + int ret; + u8 cmd; + + cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: unable to claim SPI bus\n"); + return ret; + } + + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); + return ret; + } + + return spi_flash_cmd(flash->spi, cmd, NULL, 0); +} +#endif + #ifdef CONFIG_SPI_FLASH_BAR static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) { @@ -160,6 +184,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) unsigned long timebase; unsigned long flags = SPI_XFER_BEGIN; int ret; + int out_of_time = 1; u8 status; u8 check_status = 0x0; u8 poll_bit = STATUS_WIP; @@ -186,22 +211,45 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) WATCHDOG_RESET(); ret = spi_xfer(spi, 8, NULL, &status, 0); - if (ret) + if (ret) { + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); return -1; + } - if ((status & poll_bit) == check_status) + if ((status & poll_bit) == check_status) { + out_of_time = 0; break; + } } while (get_timer(timebase) < timeout); spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); - if ((status & poll_bit) == check_status) - return 0; + if (out_of_time) { + /* Timed out */ + debug("SF: time out!\n"); + if (cmd == CMD_FLAG_STATUS) { + if (spi_flash_cmd_clear_flag_status(flash) < 0) + debug("SF: clear flag status failed\n"); + } + ret = -1; + } +#ifdef CONFIG_SPI_FLASH_STMICRO + else if (cmd == CMD_FLAG_STATUS) { + if (!(status & (STATUS_PROT | STATUS_ERASE))) { + ret = 0; + } else { + debug("SF: flag status error"); + ret = -1; + } - /* Timed out */ - debug("SF: time out!\n"); - return -1; + if (spi_flash_cmd_clear_flag_status(flash) < 0) { + debug("SF: clear flag status failed\n"); + ret = -1; + } + } +#endif + return ret; } int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, @@ -234,7 +282,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, ret = spi_flash_cmd_wait_ready(flash, timeout); if (ret < 0) { - debug("SF: write %s timed out\n", + debug("SF: write %s failed\n", timeout == SPI_FLASH_PROG_TIMEOUT ? "program" : "page erase"); return ret; diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 4d148d1..79b876d 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -221,6 +221,11 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, #ifdef CONFIG_SPI_FLASH_STMICRO if (params->flags & E_FSR) flash->poll_cmd = CMD_FLAG_STATUS; + + if (flash->size > SPI_FLASH_16MB_BOUN) { + if (spi_flash_cmd_4B_addr_switch(flash, 0) < 0) + debug("SF: enter 3B address mode failed\n"); + } #endif /* Configure the BAR - discover bank cmds and read current bank */