From patchwork Thu Oct 9 08:11:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tang yuantian X-Patchwork-Id: 397933 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id E34521400B6 for ; Thu, 9 Oct 2014 19:13:28 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 294D0A7439; Thu, 9 Oct 2014 10:13:18 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id G6HWROQ60CbW; Thu, 9 Oct 2014 10:13:17 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C9BB6A748F; Thu, 9 Oct 2014 10:13:15 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ED356A7419 for ; Thu, 9 Oct 2014 10:13:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z7PWatrt5wV7 for ; Thu, 9 Oct 2014 10:13:08 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bon0145.outbound.protection.outlook.com [157.56.111.145]) by theia.denx.de (Postfix) with ESMTPS id 199F4A7467 for ; Thu, 9 Oct 2014 10:13:04 +0200 (CEST) Received: from BN3PR0301CA0030.namprd03.prod.outlook.com (25.160.180.168) by DM2PR03MB576.namprd03.prod.outlook.com (10.141.84.19) with Microsoft SMTP Server (TLS) id 15.0.1044.10; Thu, 9 Oct 2014 08:13:02 +0000 Received: from BN1AFFO11FD021.protection.gbl (2a01:111:f400:7c10::184) by BN3PR0301CA0030.outlook.office365.com (2a01:111:e400:4000::40) with Microsoft SMTP Server (TLS) id 15.0.1049.19 via Frontend Transport; Thu, 9 Oct 2014 08:13:01 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD021.mail.protection.outlook.com (10.58.52.81) with Microsoft SMTP Server (TLS) id 15.0.1039.16 via Frontend Transport; Thu, 9 Oct 2014 08:13:01 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s998CEdJ011140; Thu, 9 Oct 2014 01:12:58 -0700 From: To: Date: Thu, 9 Oct 2014 16:11:38 +0800 Message-ID: <1412842298-3257-5-git-send-email-Yuantian.Tang@freescale.com> X-Mailer: git-send-email 2.1.0.27.g96db324 In-Reply-To: <1412842298-3257-1-git-send-email-Yuantian.Tang@freescale.com> References: <1412842298-3257-1-git-send-email-Yuantian.Tang@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(199003)(189002)(69596002)(77156001)(92566001)(99396003)(47776003)(76482002)(44976005)(89996001)(68736004)(105606002)(76176999)(80022003)(31966008)(36756003)(88136002)(84676001)(86152002)(92726001)(120916001)(50466002)(87286001)(21056001)(19580405001)(19580395003)(20776003)(48376002)(50986999)(46102003)(85852003)(87936001)(85306004)(62966002)(106466001)(81156004)(104166001)(102836001)(86362001)(93916002)(6806004)(4396001)(64706001)(107046002)(104016003)(95666004)(97736003)(26826002)(2351001)(110136001)(229853001)(50226001); DIR:OUT; SFP:1102; SCL:1; SRVR:DM2PR03MB576; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:DM2PR03MB576; X-Forefront-PRVS: 0359162B6D Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Yuantian.Tang@freescale.com; X-OriginatorOrg: freescale.com Cc: r64188@freescale.com, u-boot@lists.denx.de, yorksun@freescale.com Subject: [U-Boot] [PATCH 4/4] arm: ls1021qds: Add deep sleep support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Tang Yuantian Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian --- board/freescale/ls1021aqds/ddr.c | 7 ++++ board/freescale/ls1021aqds/ls1021aqds.c | 60 +++++++++++++++++++++++++++++++++ include/configs/ls1021aqds.h | 4 +++ 3 files changed, 71 insertions(+) diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 5898e33..6dad4cc 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -8,6 +8,9 @@ #include #include #include "ddr.h" +#ifdef CONFIG_FSL_DEEP_SLEEP +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -156,6 +159,10 @@ phys_size_t initdram(int board_type) puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); +#ifdef CONFIG_FSL_DEEP_SLEEP + fsl_dp_ddr_restore(); +#endif + return dram_size; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 12e83f7..e9dce36 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -253,3 +253,63 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } + +#ifdef CONFIG_FSL_DEEP_SLEEP +/* determine if it is a warm boot */ +bool is_warm_boot(void) +{ +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_mem_setup(void) +{ + /* does not provide HW signals for power management */ + QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); + udelay(1); +} + +void fsl_dp_ddr_restore(void) +{ +#define DDR_BUFF_LEN 128 + u64 *src, *dst; + int i; + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + if (!is_warm_boot()) + return; + + /* get the address of ddr date from SPARECR3, little endian */ + src = (u64 *)in_le32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + if (!is_warm_boot()) + return 0; + + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); + armv7_init_nonsec(); + cleanup_before_linux(); + + /* Get the entry address and jump to kernel */ + start_addr = in_le32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); + + return 0; +} +#endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index bb47813..448a07e 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -19,6 +19,10 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_FSL_DEEP_SLEEP +#ifdef CONFIG_FSL_DEEP_SLEEP +#define CONFIG_SILENT_CONSOLE +#endif /* * Size of malloc() pool */