| Message ID | 1412221423-10752-2-git-send-email-sjg@chromium.org |
|---|---|
| State | Changes Requested |
| Delegated to: | Minkyu Kang |
| Headers | show |
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 3ed70a8..207782e 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -32,7 +32,7 @@ mem-manuf = "samsung"; mem-type = "ddr3"; clock-frequency = <800000000>; - arm-frequency = <1700000000>; + arm-frequency = <900000000>; }; tmu@10060000 {
The device seems to hang in SPL if the full speed is used when booting from USB, perhaps because the PMIC has not been set to the maximum ARM core voltage yet. Slow it down to a reliable speed. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: - Add new patch to use 900MHz ARM frequeny in SPL for peach_pit arch/arm/dts/exynos5420-peach-pit.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)