From patchwork Sun Sep 21 13:12:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 391679 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 38EE81400BE for ; Sun, 21 Sep 2014 23:14:04 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BD639A7483; Sun, 21 Sep 2014 15:14:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id WvpCWGjGm8b1; Sun, 21 Sep 2014 15:14:02 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 863F7A74CE; Sun, 21 Sep 2014 15:13:07 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4BCBA4B6A7 for ; Sun, 21 Sep 2014 15:12:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id csCLwzRpHQ0y for ; Sun, 21 Sep 2014 15:12:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by theia.denx.de (Postfix) with ESMTPS id 1587C4B68A for ; Sun, 21 Sep 2014 15:12:48 +0200 (CEST) Received: from mail.nefkom.net (unknown [192.168.8.184]) by mail-out.m-online.net (Postfix) with ESMTP id 3j18Mz646rz3hlq4; Sun, 21 Sep 2014 15:12:47 +0200 (CEST) X-Auth-Info: Y7of8GkHB2aMEcmlJYPmubSoD4GEr2zQWKJoVPLMei0= Received: from chi.lan (host-82-135-33-74.customer.m-online.net [82.135.33.74]) by smtp-auth.mnet-online.de (Postfix) with ESMTPA id 3j18Mz1tn0zvhTZ; Sun, 21 Sep 2014 15:12:47 +0200 (CEST) From: Marek Vasut To: u-boot@lists.denx.de Date: Sun, 21 Sep 2014 15:12:16 +0200 Message-Id: <1411305152-11690-8-git-send-email-marex@denx.de> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1411305152-11690-1-git-send-email-marex@denx.de> References: <1411304339-11348-1-git-send-email-marex@denx.de> <1411305152-11690-1-git-send-email-marex@denx.de> Cc: Marek Vasut , Pavel Machek , Chin Liang See , Tom Rini , sr@denx.de, Dinh Nguyen Subject: [U-Boot] [PATCH 35/51] arm: socfpga: reset: Add function to reset FPGA bridges X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/cpu/armv7/socfpga/reset_manager.c | 38 +++++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 2 ++ 2 files changed, 40 insertions(+) diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index badc569..1d3a95d 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +51,43 @@ void reset_deassert_peripherals_handoff(void) writel(0, &reset_manager_base->per_mod_reset); } +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +void socfpga_bridges_reset(int enable) +{ + /* For SoCFPGA-VT, this is NOP. */ +} +#else + +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 +#define L3REGS_REMAP_OCRAM_MASK 0x01 + +void socfpga_bridges_reset(int enable) +{ + const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | + L3REGS_REMAP_HPS2FPGA_MASK | + L3REGS_REMAP_OCRAM_MASK; + + if (enable) { + /* brdmodrst */ + writel(0xffffffff, &reset_manager_base->brg_mod_reset); + } else { + /* Check signal from FPGA. */ + if (fpgamgr_poll_fpga_ready()) { + /* FPGA not ready. Wait for watchdog timeout. */ + printf("%s: fpga not ready, hanging.\n", __func__); + hang(); + } + + /* brdmodrst */ + writel(0, &reset_manager_base->brg_mod_reset); + + /* Remap the bridges into memory map */ + writel(l3mask, SOCFPGA_L3REGS_ADDRESS); + } +} +#endif + /* Change the reset state for EMAC 0 and EMAC 1 */ void socfpga_emac_reset(int enable) { diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index 3c5ab40..1857b80 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -10,6 +10,8 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_reset(int enable); + void socfpga_emac_reset(int enable); void socfpga_watchdog_reset(void);