Message ID | 1410400455-9992-1-git-send-email-Peng.Fan@freescale.com |
---|---|
State | Changes Requested |
Delegated to: | Stefano Babic |
Headers | show |
Hi, just ping, Any comments about this patch? Regards, Peng. On 09/11/2014 09:54 AM, Peng Fan wrote: > Add QSPI support for mx6solox. > > Signed-off-by: Peng Fan <Peng.Fan@freescale.com> > --- > > Changelog v2: > Take Fabio's suggestion, split soc code and board code into two patches. > > arch/arm/cpu/armv7/mx6/clock.c | 50 +++++++++++++++++++++++++++++++++++ > arch/arm/include/asm/arch-mx6/clock.h | 3 +++ > drivers/spi/fsl_qspi.c | 29 ++++++++++++++++++++ > 3 files changed, 82 insertions(+) > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > index 820b8d5..8caa61d 100644 > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void) > } > #endif > > +#ifdef CONFIG_MX6SX > +/* qspi_num can be from 0 - 1 */ > +void enable_qspi_clk(int qspi_num) > +{ > + u32 reg = 0; > + /* Enable QuadSPI clock */ > + switch (qspi_num) { > + case 0: > + /* disable the clock gate */ > + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); > + > + /* set 50M : (50 = 396 / 2 / 4) */ > + reg = readl(&imx_ccm->cscmr1); > + reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | > + MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); > + reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | > + (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); > + writel(reg, &imx_ccm->cscmr1); > + > + /* enable the clock gate */ > + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); > + break; > + case 1: > + /* > + * disable the clock gate > + * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, > + * disable both of them. > + */ > + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | > + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); > + > + /* set 50M : (50 = 396 / 2 / 4) */ > + reg = readl(&imx_ccm->cs2cdr); > + reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | > + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | > + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); > + reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | > + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); > + writel(reg, &imx_ccm->cs2cdr); > + > + /*enable the clock gate*/ > + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | > + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); > + break; > + default: > + break; > + } > +} > +#endif > + > #ifdef CONFIG_FEC_MXC > int enable_fec_anatop_clock(enum enet_freq freq) > { > diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h > index 339c789..9d0ba7a 100644 > --- a/arch/arm/include/asm/arch-mx6/clock.h > +++ b/arch/arm/include/asm/arch-mx6/clock.h > @@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num); > int enable_spi_clk(unsigned char enable, unsigned spi_num); > void enable_ipu_clock(void); > int enable_fec_anatop_clock(enum enet_freq freq); > +#ifdef CONFIG_MX6SX > +void enable_qspi_clk(int qspi_num); > +#endif > #endif /* __ASM_ARCH_CLOCK_H */ > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c > index ba20bef..7c8d065 100644 > --- a/drivers/spi/fsl_qspi.c > +++ b/drivers/spi/fsl_qspi.c > @@ -14,7 +14,11 @@ > #include "fsl_qspi.h" > > #define RX_BUFFER_SIZE 0x80 > +#ifdef CONFIG_MX6SX > +#define TX_BUFFER_SIZE 0x200 > +#else > #define TX_BUFFER_SIZE 0x40 > +#endif > > #define OFFSET_BITS_MASK 0x00ffffff > > @@ -52,11 +56,19 @@ > #endif > > static unsigned long spi_bases[] = { > +#ifdef CONFIG_MX6SX > + CONFIG_QSPI_BASE, > +#else > QSPI0_BASE_ADDR, > +#endif > }; > > static unsigned long amba_bases[] = { > +#ifdef CONFIG_MX6SX > + CONFIG_QSPI_MEMMAP_BASE, > +#else > QSPI0_AMBA_BASE, > +#endif > }; > > struct fsl_qspi { > @@ -157,8 +169,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi) > qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP_4B) | > PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | > PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); > +#ifdef CONFIG_MX6SX > + /* Use IDATSZ in IPCR to determine the size */ > + qspi_write32(®s->lut[lut_base + 1], OPRND0(0) | > + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); > +#else > qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | > PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); > +#endif > qspi_write32(®s->lut[lut_base + 2], 0); > qspi_write32(®s->lut[lut_base + 3], 0); > > @@ -192,6 +210,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, > if (bus >= ARRAY_SIZE(spi_bases)) > return NULL; > > +#ifdef CONFIG_MX6SX > + /* cs should be 0 - (FSL_QSPI_FLASH_NUM - 1) */ > + if (cs >= FSL_QSPI_FLASH_NUM) > + return NULL; > +#endif > + > qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); > if (!qspi) > return NULL; > @@ -215,6 +239,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, > qspi_write32(®s->sfb1ad, total_size | qspi->amba_base); > qspi_write32(®s->sfb2ad, total_size | qspi->amba_base); > > +#ifdef CONFIG_MX6SX > + /* According to cs, change the amba_base to choose the flash */ > + qspi->amba_base = qspi->amba_base + cs * FSL_QSPI_FLASH_SIZE; > +#endif > + > qspi_set_lut(qspi); > > smpr_val = qspi_read32(®s->smpr); >
Hi Peng, On Thu, 9 Oct 2014 17:08:10 +0800, Peng Fan <B51431@freescale.com> wrote: > Hi, > > just ping, Any comments about this patch? > > Regards, > Peng. > On 09/11/2014 09:54 AM, Peng Fan wrote: > > Add QSPI support for mx6solox. > > > > Signed-off-by: Peng Fan <Peng.Fan@freescale.com> > > --- > > > > Changelog v2: > > Take Fabio's suggestion, split soc code and board code into two patches. > > > > arch/arm/cpu/armv7/mx6/clock.c | 50 +++++++++++++++++++++++++++++++++++ > > arch/arm/include/asm/arch-mx6/clock.h | 3 +++ > > drivers/spi/fsl_qspi.c | 29 ++++++++++++++++++++ > > 3 files changed, 82 insertions(+) > > > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > > index 820b8d5..8caa61d 100644 > > --- a/arch/arm/cpu/armv7/mx6/clock.c > > +++ b/arch/arm/cpu/armv7/mx6/clock.c > > @@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void) > > } > > #endif > > > > +#ifdef CONFIG_MX6SX > > +/* qspi_num can be from 0 - 1 */ > > +void enable_qspi_clk(int qspi_num) > > +{ > > + u32 reg = 0; > > + /* Enable QuadSPI clock */ > > + switch (qspi_num) { > > + case 0: > > + /* disable the clock gate */ > > + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); > > + > > + /* set 50M : (50 = 396 / 2 / 4) */ > > + reg = readl(&imx_ccm->cscmr1); > > + reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | > > + MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); > > + reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | > > + (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); > > + writel(reg, &imx_ccm->cscmr1); > > + > > + /* enable the clock gate */ > > + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); > > + break; > > + case 1: > > + /* > > + * disable the clock gate > > + * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, > > + * disable both of them. > > + */ > > + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | > > + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); > > + > > + /* set 50M : (50 = 396 / 2 / 4) */ > > + reg = readl(&imx_ccm->cs2cdr); > > + reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | > > + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | > > + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); > > + reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | > > + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); > > + writel(reg, &imx_ccm->cs2cdr); > > + > > + /*enable the clock gate*/ > > + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | > > + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); > > + break; > > + default: > > + break; > > + } > > +} > > +#endif > > + > > #ifdef CONFIG_FEC_MXC > > int enable_fec_anatop_clock(enum enet_freq freq) > > { > > diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h > > index 339c789..9d0ba7a 100644 > > --- a/arch/arm/include/asm/arch-mx6/clock.h > > +++ b/arch/arm/include/asm/arch-mx6/clock.h > > @@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num); > > int enable_spi_clk(unsigned char enable, unsigned spi_num); > > void enable_ipu_clock(void); > > int enable_fec_anatop_clock(enum enet_freq freq); > > +#ifdef CONFIG_MX6SX > > +void enable_qspi_clk(int qspi_num); > > +#endif > > #endif /* __ASM_ARCH_CLOCK_H */ > > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c > > index ba20bef..7c8d065 100644 > > --- a/drivers/spi/fsl_qspi.c > > +++ b/drivers/spi/fsl_qspi.c > > @@ -14,7 +14,11 @@ > > #include "fsl_qspi.h" > > > > #define RX_BUFFER_SIZE 0x80 > > +#ifdef CONFIG_MX6SX > > +#define TX_BUFFER_SIZE 0x200 > > +#else > > #define TX_BUFFER_SIZE 0x40 > > +#endif > > > > #define OFFSET_BITS_MASK 0x00ffffff > > > > @@ -52,11 +56,19 @@ > > #endif > > > > static unsigned long spi_bases[] = { > > +#ifdef CONFIG_MX6SX > > + CONFIG_QSPI_BASE, > > +#else > > QSPI0_BASE_ADDR, > > +#endif > > }; > > > > static unsigned long amba_bases[] = { > > +#ifdef CONFIG_MX6SX > > + CONFIG_QSPI_MEMMAP_BASE, > > +#else > > QSPI0_AMBA_BASE, > > +#endif > > }; > > > > struct fsl_qspi { > > @@ -157,8 +169,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi) > > qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP_4B) | > > PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | > > PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); > > +#ifdef CONFIG_MX6SX > > + /* Use IDATSZ in IPCR to determine the size */ > > + qspi_write32(®s->lut[lut_base + 1], OPRND0(0) | > > + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); > > +#else > > qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | > > PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); > > +#endif > > qspi_write32(®s->lut[lut_base + 2], 0); > > qspi_write32(®s->lut[lut_base + 3], 0); > > > > @@ -192,6 +210,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, > > if (bus >= ARRAY_SIZE(spi_bases)) > > return NULL; > > > > +#ifdef CONFIG_MX6SX > > + /* cs should be 0 - (FSL_QSPI_FLASH_NUM - 1) */ > > + if (cs >= FSL_QSPI_FLASH_NUM) > > + return NULL; > > +#endif > > + > > qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); > > if (!qspi) > > return NULL; > > @@ -215,6 +239,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, > > qspi_write32(®s->sfb1ad, total_size | qspi->amba_base); > > qspi_write32(®s->sfb2ad, total_size | qspi->amba_base); > > > > +#ifdef CONFIG_MX6SX > > + /* According to cs, change the amba_base to choose the flash */ > > + qspi->amba_base = qspi->amba_base + cs * FSL_QSPI_FLASH_SIZE; > > +#endif > > + > > qspi_set_lut(qspi); > > > > smpr_val = qspi_read32(®s->smpr); > > Jagan said he would review both patches. Once he gives his Acked-by, the patches will go in -- but note that the series is an addition, not a fix, and came in after the 2014.10 merge window, so it'll go in only after the upcoming release (that's only a few days anyway). Amicalement,
Hi Jagan, On Fri, Oct 10, 2014 at 6:58 AM, Albert ARIBAUD <albert.u.boot@aribaud.net> wrote: > Jagan said he would review both patches. Once he gives his Acked-by, > the patches will go in -- but note that the series is an addition, not > a fix, and came in after the 2014.10 merge window, so it'll go in only > after the upcoming release (that's only a few days anyway). Any comments about this series, please?
On 29 December 2014 at 23:58, Fabio Estevam <festevam@gmail.com> wrote: > Hi Jagan, > > On Fri, Oct 10, 2014 at 6:58 AM, Albert ARIBAUD > <albert.u.boot@aribaud.net> wrote: > >> Jagan said he would review both patches. Once he gives his Acked-by, >> the patches will go in -- but note that the series is an addition, not >> a fix, and came in after the 2014.10 merge window, so it'll go in only >> after the upcoming release (that's only a few days anyway). > > Any comments about this series, please? I believe there is a v3 series for this - will comment those. thanks!
Hi Peng/Fabio, On 30 December 2014 at 00:14, Jagan Teki <jagannadh.teki@gmail.com> wrote: > On 29 December 2014 at 23:58, Fabio Estevam <festevam@gmail.com> wrote: >> Hi Jagan, >> >> On Fri, Oct 10, 2014 at 6:58 AM, Albert ARIBAUD >> <albert.u.boot@aribaud.net> wrote: >> >>> Jagan said he would review both patches. Once he gives his Acked-by, >>> the patches will go in -- but note that the series is an addition, not >>> a fix, and came in after the 2014.10 merge window, so it'll go in only >>> after the upcoming release (that's only a few days anyway). >> >> Any comments about this series, please? > > I believe there is a v3 series for this - will comment those. These are v3 series for this patches- https://patchwork.ozlabs.org/patch/399361/ https://patchwork.ozlabs.org/patch/399362/ https://patchwork.ozlabs.org/patch/399363/ https://patchwork.ozlabs.org/patch/399364/ Please confirm? thanks!
Hi Jagan, On Tue, Dec 30, 2014 at 10:49 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > These are v3 series for this patches- > https://patchwork.ozlabs.org/patch/399361/ > https://patchwork.ozlabs.org/patch/399362/ > https://patchwork.ozlabs.org/patch/399363/ > https://patchwork.ozlabs.org/patch/399364/ > > Please confirm? That's correct. Please let us know if you have comments about v3. Thanks
On 30 December 2014 at 18:32, Fabio Estevam <festevam@gmail.com> wrote: > Hi Jagan, > > On Tue, Dec 30, 2014 at 10:49 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > >> These are v3 series for this patches- >> https://patchwork.ozlabs.org/patch/399361/ >> https://patchwork.ozlabs.org/patch/399362/ >> https://patchwork.ozlabs.org/patch/399363/ >> https://patchwork.ozlabs.org/patch/399364/ >> >> Please confirm? > > That's correct. Please let us know if you have comments about v3. Please rebase and send the patches again, I have some issues while applying. I will pick these on my tree. thanks!
On Tue, Dec 30, 2014 at 11:16 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > Please rebase and send the patches again, I have some issues while applying. > I will pick these on my tree. Peng, please rebase and resend the series. Thanks
Hi, On 12/30/2014 9:19 PM, Fabio Estevam wrote: > On Tue, Dec 30, 2014 at 11:16 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > >> Please rebase and send the patches again, I have some issues while applying. >> I will pick these on my tree. > > Peng, please rebase and resend the series. Thanks > After rebasing, I sent a v4 patch set. Please review. Thanks, Peng Fan.
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 820b8d5..8caa61d 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void) } #endif +#ifdef CONFIG_MX6SX +/* qspi_num can be from 0 - 1 */ +void enable_qspi_clk(int qspi_num) +{ + u32 reg = 0; + /* Enable QuadSPI clock */ + switch (qspi_num) { + case 0: + /* disable the clock gate */ + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cscmr1); + reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK | + MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK); + reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) | + (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)); + writel(reg, &imx_ccm->cscmr1); + + /* enable the clock gate */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); + break; + case 1: + /* + * disable the clock gate + * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, + * disable both of them. + */ + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + + /* set 50M : (50 = 396 / 2 / 4) */ + reg = readl(&imx_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK); + reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3)); + writel(reg, &imx_ccm->cs2cdr); + + /*enable the clock gate*/ + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); + break; + default: + break; + } +} +#endif + #ifdef CONFIG_FEC_MXC int enable_fec_anatop_clock(enum enet_freq freq) { diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 339c789..9d0ba7a 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); +#ifdef CONFIG_MX6SX +void enable_qspi_clk(int qspi_num); +#endif #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index ba20bef..7c8d065 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -14,7 +14,11 @@ #include "fsl_qspi.h" #define RX_BUFFER_SIZE 0x80 +#ifdef CONFIG_MX6SX +#define TX_BUFFER_SIZE 0x200 +#else #define TX_BUFFER_SIZE 0x40 +#endif #define OFFSET_BITS_MASK 0x00ffffff @@ -52,11 +56,19 @@ #endif static unsigned long spi_bases[] = { +#ifdef CONFIG_MX6SX + CONFIG_QSPI_BASE, +#else QSPI0_BASE_ADDR, +#endif }; static unsigned long amba_bases[] = { +#ifdef CONFIG_MX6SX + CONFIG_QSPI_MEMMAP_BASE, +#else QSPI0_AMBA_BASE, +#endif }; struct fsl_qspi { @@ -157,8 +169,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi) qspi_write32(®s->lut[lut_base], OPRND0(OPCODE_PP_4B) | PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); +#ifdef CONFIG_MX6SX + /* Use IDATSZ in IPCR to determine the size */ + qspi_write32(®s->lut[lut_base + 1], OPRND0(0) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); +#else qspi_write32(®s->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); +#endif qspi_write32(®s->lut[lut_base + 2], 0); qspi_write32(®s->lut[lut_base + 3], 0); @@ -192,6 +210,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (bus >= ARRAY_SIZE(spi_bases)) return NULL; +#ifdef CONFIG_MX6SX + /* cs should be 0 - (FSL_QSPI_FLASH_NUM - 1) */ + if (cs >= FSL_QSPI_FLASH_NUM) + return NULL; +#endif + qspi = spi_alloc_slave(struct fsl_qspi, bus, cs); if (!qspi) return NULL; @@ -215,6 +239,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, qspi_write32(®s->sfb1ad, total_size | qspi->amba_base); qspi_write32(®s->sfb2ad, total_size | qspi->amba_base); +#ifdef CONFIG_MX6SX + /* According to cs, change the amba_base to choose the flash */ + qspi->amba_base = qspi->amba_base + cs * FSL_QSPI_FLASH_SIZE; +#endif + qspi_set_lut(qspi); smpr_val = qspi_read32(®s->smpr);
Add QSPI support for mx6solox. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> --- Changelog v2: Take Fabio's suggestion, split soc code and board code into two patches. arch/arm/cpu/armv7/mx6/clock.c | 50 +++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 3 +++ drivers/spi/fsl_qspi.c | 29 ++++++++++++++++++++ 3 files changed, 82 insertions(+)