From patchwork Tue Aug 19 20:28:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 381481 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6F8021400D5 for ; Wed, 20 Aug 2014 06:28:59 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E57964B5FD; Tue, 19 Aug 2014 22:28:45 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id J99Hzpj8Dcxg; Tue, 19 Aug 2014 22:28:45 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6EFAD4B601; Tue, 19 Aug 2014 22:28:27 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9BF094A01F for ; Tue, 19 Aug 2014 22:28:20 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id FfwzVapcOXhI for ; Tue, 19 Aug 2014 22:28:16 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1lp0144.outbound.protection.outlook.com [207.46.163.144]) by theia.denx.de (Postfix) with ESMTPS id 1D1674B5B9 for ; Tue, 19 Aug 2014 22:28:12 +0200 (CEST) Received: from CH1PR03CA010.namprd03.prod.outlook.com (10.255.156.155) by BY2PR03MB315.namprd03.prod.outlook.com (10.141.139.25) with Microsoft SMTP Server (TLS) id 15.0.1010.13; Tue, 19 Aug 2014 20:28:08 +0000 Received: from BL2FFO11FD050.protection.gbl (10.255.156.132) by CH1PR03CA010.outlook.office365.com (10.255.156.155) with Microsoft SMTP Server (TLS) id 15.0.1010.18 via Frontend Transport; Tue, 19 Aug 2014 20:28:07 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD050.mail.protection.outlook.com (10.173.161.212) with Microsoft SMTP Server (TLS) id 15.0.1010.11 via Frontend Transport; Tue, 19 Aug 2014 20:28:07 +0000 Received: from oslab-l1.am.freescale.net ([10.214.85.130]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s7JKS1Bv025588; Tue, 19 Aug 2014 13:28:05 -0700 From: York Sun To: Date: Tue, 19 Aug 2014 13:28:01 -0700 Message-ID: <1408480082-4617-4-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1408480082-4617-1-git-send-email-yorksun@freescale.com> References: <1408480082-4617-1-git-send-email-yorksun@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019006)(979002)(6009001)(189002)(199003)(54534003)(107046002)(87286001)(106466001)(77156001)(105606002)(97736001)(86362001)(81156004)(47776003)(74662001)(104166001)(19580395003)(50986999)(50226001)(2351001)(62966002)(110136001)(76176999)(31966008)(4396001)(69596002)(36756003)(50466002)(6806004)(64706001)(44976005)(95666004)(19580405001)(229853001)(20776003)(83322001)(84676001)(74502001)(85306004)(79102001)(85852003)(76482001)(80022001)(83072002)(88136002)(89996001)(81342001)(81542001)(77982001)(93916002)(48376002)(102836001)(92726001)(33646002)(46102001)(26826002)(87936001)(99396002)(68736004)(92566001)(104016003)(21056001)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR03MB315; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 0308EE423E Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=yorksun@freescale.com; X-OriginatorOrg: freescale.com Cc: trini@ti.com, scottwood@freescale.com, York Sun Subject: [U-Boot] [Patch v2 4/5] ARMv8/ls2085a: Enable secondary cores X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun Signed-off-by: Arnab Basu --- Change log v2: Use individual spin table for each core by default board/freescale/ls2085a/ls2085a.c | 2 ++ include/configs/ls2085a_common.h | 9 ++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index a18db1d..3daa787 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -88,6 +88,8 @@ void ft_board_setup(void *blob, bd_t *bd) phys_addr_t base; phys_size_t size; + ft_cpu_setup(blob, bd); + /* limit the memory size to bank 1 until Linux can handle 40-bit PA */ base = getenv_bootm_low(); size = getenv_bootm_size(); diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 2bd5a47..4c258ca 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -45,14 +45,16 @@ #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ -/* SMP Definitions */ -#define CPU_RELEASE_ADDR CONFIG_SYS_INIT_SP_ADDR - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL +/* + * SMP Definitions + */ +#define CPU_RELEASE_ADDR secondary_boot_func + /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 12000000 /* 12MHz */ @@ -167,6 +169,7 @@ /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) +#define CONFIG_ARCH_EARLY_INIT_R /* Physical Memory Map */ /* fixme: these need to be checked against the board */