Message ID | 1407051288-17324-11-git-send-email-nikita@compulab.co.il |
---|---|
State | Changes Requested |
Delegated to: | Stefano Babic |
Headers | show |
On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov <nikita@compulab.co.il> wrote: > According to MX6 TRM, both MMDC and DRAM should be configured to > the same powerdown precharge. Currently, mx6_dram_cfg() > configures MMDC for fast pd, and the DRAM for slow pd. Nikita, I'm inclined to agree with you. A glance at some of the existing non-spl board config's show this same discrepancy which probably comes form an error in the IMX DDR3 Script Aid spreadsheet (https://community.freescale.com/docs/DOC-94917). I would at least add to the description the fact that the precharge pd is MR0 bit12 for DRAM and the current value of 0 indicates 'Slow exit (DLL off)'. I've asked our Freescale FAE for clarification to see if the spreadsheet is in error. Regards, Tim > > Configure MMDC for slow pd. > > Cc: Stefano Babic <sbabic@denx.de> > Cc: Tim Harvey <tharvey@gateworks.com> > Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> > --- > arch/arm/cpu/armv7/mx6/ddr.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c > index 70ce38f..c0fb749 100644 > --- a/arch/arm/cpu/armv7/mx6/ddr.c > +++ b/arch/arm/cpu/armv7/mx6/ddr.c > @@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, > mmdc0->mdpdc = (tcke & 0x7) << 16 | > 5 << 12 | /* PWDT_1: 256 cycles */ > 5 << 8 | /* PWDT_0: 256 cycles */ > + 1 << 7 | /* SLOW_PD */ > 1 << 6 | /* BOTH_CS_PD */ > (tcksrx & 0x7) << 3 | > (tcksre & 0x7); > -- > 1.9.1 >
On 04/08/14 08:42, Tim Harvey wrote: > On Sun, Aug 3, 2014 at 12:34 AM, Nikita Kiryanov <nikita@compulab.co.il> wrote: >> According to MX6 TRM, both MMDC and DRAM should be configured to >> the same powerdown precharge. Currently, mx6_dram_cfg() >> configures MMDC for fast pd, and the DRAM for slow pd. > > Nikita, > > I'm inclined to agree with you. A glance at some of the existing > non-spl board config's show this same discrepancy which probably comes > form an error in the IMX DDR3 Script Aid spreadsheet > (https://community.freescale.com/docs/DOC-94917). > > I would at least add to the description the fact that the precharge pd > is MR0 bit12 for DRAM and the current value of 0 indicates 'Slow exit > (DLL off)'. I've asked our Freescale FAE for clarification to see if > the spreadsheet is in error. OK, I'll add it once the FAE confirms the error. > > Regards, > > Tim >
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 70ce38f..c0fb749 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mdpdc = (tcke & 0x7) << 16 | 5 << 12 | /* PWDT_1: 256 cycles */ 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 7 | /* SLOW_PD */ 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7);
According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd, and the DRAM for slow pd. Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> --- arch/arm/cpu/armv7/mx6/ddr.c | 1 + 1 file changed, 1 insertion(+)