diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index d93a991..c641cf3 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -670,23 +670,6 @@ eth_loopback_test (void)
 	immr->im_cpmux.cmx_fcr = CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11|\
 	    CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14|\
 	    CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16;
-#elif defined(CONFIG_SACSng)
-	/*
-	 * Attention: this is board-specific
-	 * 1, FCC2
-	 */
-#       define FCC_START_LOOP 1
-#       define FCC_END_LOOP   1
-
-	/*
-	 * Attention: this is board-specific
-	 * - FCC2 Rx-CLK is CLK13
-	 * - FCC2 Tx-CLK is CLK14
-	 */
-
-	/* 28.9 - (3): connect FCC's tx and rx clocks */
-	immr->im_cpmux.cmx_uar = 0;
-	immr->im_cpmux.cmx_fcr = CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14;
 #else
 #error "eth_loopback_test not supported on your board"
 #endif
diff --git a/board/sacsng/Makefile b/board/sacsng/Makefile
deleted file mode 100644
index 95e6b8d..0000000
--- a/board/sacsng/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= sacsng.o flash.o clkinit.o
diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c
deleted file mode 100644
index 2a28037..0000000
--- a/board/sacsng/clkinit.c
+++ /dev/null
@@ -1,1009 +0,0 @@
-/*
- * (C) Copyright 2002
- * Custom IDEAS, Inc. <www.cideas.com>
- * Jon Diekema <diekema@cideas.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/cpm_8260.h>
-#include <configs/sacsng.h>
-
-#include "clkinit.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int Daq64xSampling = 0;
-
-
-void Daq_BRG_Reset(uint brg)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     volatile uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-     *brg_ptr |=  CPM_BRG_RST;
-     *brg_ptr &= ~CPM_BRG_RST;
-}
-
-void Daq_BRG_Disable(uint brg)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     volatile uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-     *brg_ptr &= ~CPM_BRG_EN;
-}
-
-void Daq_BRG_Enable(uint brg)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     volatile uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-     *brg_ptr |= CPM_BRG_EN;
-}
-
-uint Daq_BRG_Get_Div16(uint brg)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-
-     if (*brg_ptr & CPM_BRG_DIV16) {
-	 /* DIV16 active */
-	 return true;
-     }
-     else {
-	 /* DIV16 inactive */
-	 return false;
-     }
-}
-
-void Daq_BRG_Set_Div16(uint brg, uint div16)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-
-     if (div16) {
-	 /* DIV16 active */
-	 *brg_ptr |=  CPM_BRG_DIV16;
-     }
-     else {
-	 /* DIV16 inactive */
-	 *brg_ptr &= ~CPM_BRG_DIV16;
-     }
-}
-
-uint Daq_BRG_Get_Count(uint brg)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     uint *brg_ptr;
-     uint brg_cnt;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-
-     /* Get the clock divider
-      *
-      * Note: A clock divider of 0 means divide by 1,
-      *       therefore we need to add 1 to the count.
-      */
-     brg_cnt = (*brg_ptr & CPM_BRG_CD_MASK) >> CPM_BRG_DIV16_SHIFT;
-     brg_cnt++;
-     if (*brg_ptr & CPM_BRG_DIV16) {
-	 brg_cnt *= 16;
-     }
-
-    return (brg_cnt);
-}
-
-void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-
-     /*
-      * Note: A clock divider of 0 means divide by 1,
-      *	 therefore we need to subtract 1 from the count.
-      */
-     if (brg_cnt > 4096) {
-	 /* Prescale = Divide by 16 */
-	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK)   |
-	     (((brg_cnt / 16) - 1) << CPM_BRG_DIV16_SHIFT);
-	 *brg_ptr |= CPM_BRG_DIV16;
-     }
-     else {
-	 /* Prescale = Divide by 1 */
-	 *brg_ptr = (*brg_ptr & ~CPM_BRG_CD_MASK) |
-	     ((brg_cnt - 1) << CPM_BRG_DIV16_SHIFT);
-	 *brg_ptr &= ~CPM_BRG_DIV16;
-     }
-}
-
-uint Daq_BRG_Get_ExtClk(uint brg)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-
-     return ((*brg_ptr & CPM_BRG_EXTC_MASK) >> CPM_BRG_EXTC_SHIFT);
-}
-
-char* Daq_BRG_Get_ExtClk_Description(uint brg)
-{
-     uint extc;
-
-     extc = Daq_BRG_Get_ExtClk(brg);
-
-     switch (brg + 1) {
-	 case 1:
-	 case 2:
-	 case 5:
-	 case 6: {
-	     switch (extc) {
-		 case 0: {
-		     return ("BRG_INT");
-		 }
-		 case 1: {
-		     return ("CLK3");
-		 }
-		 case 2: {
-		     return ("CLK5");
-		 }
-	     }
-	     return ("??1245??");
-	 }
-	 case 3:
-	 case 4:
-	 case 7:
-	 case 8: {
-	     switch (extc) {
-		 case 0: {
-		     return ("BRG_INT");
-		 }
-		 case 1: {
-		     return ("CLK9");
-		 }
-		 case 2: {
-		     return ("CLK15");
-		 }
-	     }
-	     return ("??3478??");
-	 }
-     }
-     return ("??9876??");
-}
-
-void Daq_BRG_Set_ExtClk(uint brg, uint extc)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     uint *brg_ptr;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg -= 4;
-     }
-     brg_ptr += brg;
-
-     *brg_ptr = (*brg_ptr & ~CPM_BRG_EXTC_MASK) |
-		((extc << CPM_BRG_EXTC_SHIFT) & CPM_BRG_EXTC_MASK);
-}
-
-uint Daq_BRG_Rate(uint brg)
-{
-     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-     uint *brg_ptr;
-     uint brg_cnt;
-     uint brg_freq = 0;
-
-     brg_ptr = (uint *)&immr->im_brgc1;
-     brg_ptr += brg;
-     if (brg >= 5) {
-	 brg_ptr = (uint *)&immr->im_brgc5;
-	 brg_ptr += (brg - 4);
-     }
-
-    brg_cnt = Daq_BRG_Get_Count(brg);
-
-    switch (Daq_BRG_Get_ExtClk(brg)) {
-	case CPM_BRG_EXTC_CLK3:
-	case CPM_BRG_EXTC_CLK5: {
-	    brg_freq = brg_cnt;
-	    break;
-	}
-	default: {
-	    brg_freq = (uint)BRG_INT_CLK / brg_cnt;
-	}
-    }
-    return (brg_freq);
-}
-
-uint Daq_Get_SampleRate(void)
-{
-     /*
-      * Read the BRG's to return the actual sample rate.
-      */
-     return (Daq_BRG_Rate(MCLK_BRG) / (MCLK_DIVISOR * SCLK_DIVISOR));
-}
-
-void Daq_Init_Clocks(int sample_rate, int sample_64x)
-{
-    volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
-    uint mclk_divisor; /* MCLK divisor */
-    int  flag;         /* Interrupt state */
-
-    /* Save off the clocking data */
-    Daq64xSampling = sample_64x;
-
-    /*
-     * Limit the sample rate to some sensible values.
-     */
-    if (sample_rate > MAX_64x_SAMPLE_RATE) {
-	sample_rate = MAX_64x_SAMPLE_RATE;
-    }
-    if (sample_rate < MIN_SAMPLE_RATE) {
-	sample_rate = MIN_SAMPLE_RATE;
-    }
-
-    /*
-     * Initialize the MCLK/SCLK/LRCLK baud rate generators.
-     */
-
-    /* Setup MCLK */
-    Daq_BRG_Set_ExtClk(MCLK_BRG, CPM_BRG_EXTC_BRGCLK);
-
-    /* Setup SCLK */
-#   ifdef RUN_SCLK_ON_BRG_INT
-	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_BRGCLK);
-#   else
-	Daq_BRG_Set_ExtClk(SCLK_BRG, CPM_BRG_EXTC_CLK9);
-#   endif
-
-    /* Setup LRCLK */
-#   ifdef RUN_LRCLK_ON_BRG_INT
-	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_BRGCLK);
-#   else
-	Daq_BRG_Set_ExtClk(LRCLK_BRG, CPM_BRG_EXTC_CLK5);
-#   endif
-
-    /*
-     * Dynamically adjust MCLK based on the new sample rate.
-     */
-
-    /* Compute the divisors */
-    mclk_divisor = BRG_INT_CLK / (sample_rate * MCLK_DIVISOR * SCLK_DIVISOR);
-
-    /*
-     * Disable interrupt and save the current state
-     */
-    flag = disable_interrupts();
-
-    /* Setup MCLK */
-    Daq_BRG_Set_Count(MCLK_BRG, mclk_divisor);
-
-    /* Setup SCLK */
-#   ifdef RUN_SCLK_ON_BRG_INT
-	Daq_BRG_Set_Count(SCLK_BRG, mclk_divisor * MCLK_DIVISOR);
-#   else
-	Daq_BRG_Set_Count(SCLK_BRG, MCLK_DIVISOR);
-#   endif
-
-#   ifdef RUN_LRCLK_ON_BRG_INT
-	Daq_BRG_Set_Count(LRCLK_BRG,
-			  mclk_divisor * MCLK_DIVISOR * SCLK_DIVISOR);
-#   else
-	Daq_BRG_Set_Count(LRCLK_BRG, SCLK_DIVISOR);
-#   endif
-
-    /*
-     * Restore the Interrupt state
-     */
-     if (flag) {
-	 enable_interrupts();
-     }
-
-    /* Enable the clock drivers */
-    iopa->pdat &= ~SLRCLK_EN_MASK;
-}
-
-void Daq_Stop_Clocks(void)
-
-{
-#ifdef TIGHTEN_UP_BRG_TIMING
-    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-    register uint mclk_brg;       /* MCLK  BRG value */
-    register uint sclk_brg;       /* SCLK  BRG value */
-    register uint lrclk_brg;      /* LRCLK BRG value */
-    unsigned long flag;           /* Interrupt flags */
-#endif
-
-#   ifdef TIGHTEN_UP_BRG_TIMING
-	/*
-	 * Obtain MCLK BRG reset/disabled value
-	 */
-#       if (MCLK_BRG == 0)
-	    mclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 1)
-	    mclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 2)
-	    mclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 3)
-	    mclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 4)
-	    mclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 5)
-	    mclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 6)
-	    mclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 7)
-	    mclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-
-	/*
-	 * Obtain SCLK BRG reset/disabled value
-	 */
-#       if (SCLK_BRG == 0)
-	    sclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 1)
-	    sclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 2)
-	    sclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 3)
-	    sclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 4)
-	    sclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 5)
-	    sclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 6)
-	    sclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 7)
-	    sclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-
-	/*
-	 * Obtain LRCLK BRG reset/disabled value
-	 */
-#       if (LRCLK_BRG == 0)
-	    lrclk_brg = (*IM_BRGC1 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 1)
-	    lrclk_brg = (*IM_BRGC2 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 2)
-	    lrclk_brg = (*IM_BRGC3 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 3)
-	    lrclk_brg = (*IM_BRGC4 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 4)
-	    lrclk_brg = (*IM_BRGC5 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 5)
-	    lrclk_brg = (*IM_BRGC6 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 6)
-	    lrclk_brg = (*IM_BRGC7 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 7)
-	    lrclk_brg = (*IM_BRGC8 | CPM_BRG_RST) & ~CPM_BRG_EN;
-#       endif
-
-	/*
-	 * Disable interrupt and save the current state
-	 */
-	flag = disable_interrupts();
-
-	/*
-	 * Set reset on MCLK BRG
-	 */
-#       if (MCLK_BRG == 0)
-	    *IM_BRGC1 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 1)
-	    *IM_BRGC2 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 2)
-	    *IM_BRGC3 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 3)
-	    *IM_BRGC4 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 4)
-	    *IM_BRGC5 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 5)
-	    *IM_BRGC6 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 6)
-	    *IM_BRGC7 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 7)
-	    *IM_BRGC8 = mclk_brg;
-#       endif
-
-	/*
-	 * Set reset on SCLK BRG
-	 */
-#       if (SCLK_BRG == 0)
-	    *IM_BRGC1 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 1)
-	    *IM_BRGC2 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 2)
-	    *IM_BRGC3 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 3)
-	    *IM_BRGC4 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 4)
-	    *IM_BRGC5 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 5)
-	    *IM_BRGC6 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 6)
-	    *IM_BRGC7 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 7)
-	    *IM_BRGC8 = sclk_brg;
-#       endif
-
-	/*
-	 * Set reset on LRCLK BRG
-	 */
-#       if (LRCLK_BRG == 0)
-	    *IM_BRGC1 = lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 1)
-	    *IM_BRGC2 = lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 2)
-	    *IM_BRGC3 = lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 3)
-	    *IM_BRGC4 = lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 4)
-	    *IM_BRGC5 = lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 5)
-	    *IM_BRGC6 = lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 6)
-	    *IM_BRGC7 = lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 7)
-	    *IM_BRGC8 = lrclk_brg;
-#       endif
-
-	/*
-	 * Clear reset on MCLK BRG
-	 */
-#       if (MCLK_BRG == 0)
-	    *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (MCLK_BRG == 1)
-	    *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (MCLK_BRG == 2)
-	    *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (MCLK_BRG == 3)
-	    *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (MCLK_BRG == 4)
-	    *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (MCLK_BRG == 5)
-	    *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (MCLK_BRG == 6)
-	    *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (MCLK_BRG == 7)
-	    *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
-#       endif
-
-	/*
-	 * Clear reset on SCLK BRG
-	 */
-#       if (SCLK_BRG == 0)
-	    *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (SCLK_BRG == 1)
-	    *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (SCLK_BRG == 2)
-	    *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (SCLK_BRG == 3)
-	    *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (SCLK_BRG == 4)
-	    *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (SCLK_BRG == 5)
-	    *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (SCLK_BRG == 6)
-	    *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (SCLK_BRG == 7)
-	    *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
-#       endif
-
-	/*
-	 * Clear reset on LRCLK BRG
-	 */
-#       if (LRCLK_BRG == 0)
-	    *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (LRCLK_BRG == 1)
-	    *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (LRCLK_BRG == 2)
-	    *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (LRCLK_BRG == 3)
-	    *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (LRCLK_BRG == 4)
-	    *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (LRCLK_BRG == 5)
-	    *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (LRCLK_BRG == 6)
-	    *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-#       if (LRCLK_BRG == 7)
-	    *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
-#       endif
-
-	/*
-	 * Restore the Interrupt state
-	 */
-	if (flag) {
-	    enable_interrupts();
-	}
-#   else
-	/*
-	 * Reset the clocks
-	 */
-	Daq_BRG_Reset(MCLK_BRG);
-	Daq_BRG_Reset(SCLK_BRG);
-	Daq_BRG_Reset(LRCLK_BRG);
-#   endif
-}
-
-void Daq_Start_Clocks(int sample_rate)
-
-{
-#ifdef TIGHTEN_UP_BRG_TIMING
-    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-
-    register uint mclk_brg;       /* MCLK  BRG value */
-    register uint sclk_brg;       /* SCLK  BRG value */
-    register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
-    register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
-    uint          lrclk_brg;      /* LRCLK BRG value */
-    unsigned long flags;          /* Interrupt flags */
-    uint          sclk_cnt;       /* SCLK count */
-    uint          delay_cnt;      /* Delay count */
-#endif
-
-#   ifdef TIGHTEN_UP_BRG_TIMING
-	/*
-	 * Obtain the enabled MCLK BRG value
-	 */
-#       if (MCLK_BRG == 0)
-	    mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 1)
-	    mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 2)
-	    mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 3)
-	    mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 4)
-	    mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 5)
-	    mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 6)
-	    mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (MCLK_BRG == 7)
-	    mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-
-	/*
-	 * Obtain the enabled SCLK BRG value
-	 */
-#       if (SCLK_BRG == 0)
-	    sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 1)
-	    sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 2)
-	    sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 3)
-	    sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 4)
-	    sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 5)
-	    sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 6)
-	    sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (SCLK_BRG == 7)
-	    sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-
-	/*
-	 * Obtain the enabled LRCLK BRG value
-	 */
-#       if (LRCLK_BRG == 0)
-	    lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 1)
-	    lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 2)
-	    lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 3)
-	    lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 4)
-	    lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 5)
-	    lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 6)
-	    lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-#       if (LRCLK_BRG == 7)
-	    lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
-#       endif
-
-	/* Save off the real LRCLK value */
-	real_lrclk_brg = lrclk_brg;
-
-	/* Obtain the current SCLK count */
-	sclk_cnt  = ((sclk_brg & 0x00001FFE) >> 1) + 1;
-
-	/* Compute the delay as a function of SCLK count */
-	delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
-	if (DaqSampleRate == 43402) {
-	  delay_cnt++;
-	}
-
-	/* Clear out the count */
-	temp_lrclk_brg = sclk_brg & ~0x00001FFE;
-
-	/* Insert the count */
-	temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) &  0x00001FFE;
-
-	/*
-	 * Disable interrupt and save the current state
-	 */
-	flag = disable_interrupts();
-
-	/*
-	 * Enable MCLK BRG
-	 */
-#       if (MCLK_BRG == 0)
-	    *IM_BRGC1 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 1)
-	    *IM_BRGC2 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 2)
-	    *IM_BRGC3 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 3)
-	    *IM_BRGC4 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 4)
-	    *IM_BRGC5 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 5)
-	    *IM_BRGC6 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 6)
-	    *IM_BRGC7 = mclk_brg;
-#       endif
-#       if (MCLK_BRG == 7)
-	    *IM_BRGC8 = mclk_brg;
-#       endif
-
-	/*
-	 * Enable SCLK BRG
-	 */
-#       if (SCLK_BRG == 0)
-	    *IM_BRGC1 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 1)
-	    *IM_BRGC2 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 2)
-	    *IM_BRGC3 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 3)
-	    *IM_BRGC4 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 4)
-	    *IM_BRGC5 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 5)
-	    *IM_BRGC6 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 6)
-	    *IM_BRGC7 = sclk_brg;
-#       endif
-#       if (SCLK_BRG == 7)
-	    *IM_BRGC8 = sclk_brg;
-#       endif
-
-	/*
-	 * Enable LRCLK BRG (1st time - temporary)
-	 */
-#       if (LRCLK_BRG == 0)
-	    *IM_BRGC1 = temp_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 1)
-	    *IM_BRGC2 = temp_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 2)
-	    *IM_BRGC3 = temp_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 3)
-	    *IM_BRGC4 = temp_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 4)
-	    *IM_BRGC5 = temp_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 5)
-	    *IM_BRGC6 = temp_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 6)
-	    *IM_BRGC7 = temp_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 7)
-	    *IM_BRGC8 = temp_lrclk_brg;
-#       endif
-
-	/*
-	 * Enable LRCLK BRG (2nd time - permanent)
-	 */
-#       if (LRCLK_BRG == 0)
-	    *IM_BRGC1 = real_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 1)
-	    *IM_BRGC2 = real_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 2)
-	    *IM_BRGC3 = real_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 3)
-	    *IM_BRGC4 = real_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 4)
-	    *IM_BRGC5 = real_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 5)
-	    *IM_BRGC6 = real_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 6)
-	    *IM_BRGC7 = real_lrclk_brg;
-#       endif
-#       if (LRCLK_BRG == 7)
-	    *IM_BRGC8 = real_lrclk_brg;
-#       endif
-
-	/*
-	 * Restore the Interrupt state
-	 */
-	if (flag) {
-	    enable_interrupts();
-	}
-#   else
-	/*
-	 * Enable the clocks
-	 */
-	Daq_BRG_Enable(LRCLK_BRG);
-	Daq_BRG_Enable(SCLK_BRG);
-	Daq_BRG_Enable(MCLK_BRG);
-#   endif
-}
-
-void Daq_Display_Clocks(void)
-
-{
-    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-    uint mclk_divisor; /* Detected MCLK divisor */
-    uint sclk_divisor; /* Detected SCLK divisor */
-
-    printf("\nBRG:\n");
-    if (immr->im_brgc4 != 0) {
-	printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  MCLK\n",
-	       immr->im_brgc4,
-	       (uint)&(immr->im_brgc4),
-	       Daq_BRG_Get_Count(3),
-	       Daq_BRG_Get_ExtClk(3),
-	       Daq_BRG_Get_ExtClk_Description(3));
-    }
-    if (immr->im_brgc8 != 0) {
-	printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCLK\n",
-	       immr->im_brgc8,
-	       (uint)&(immr->im_brgc8),
-	       Daq_BRG_Get_Count(7),
-	       Daq_BRG_Get_ExtClk(7),
-	       Daq_BRG_Get_ExtClk_Description(7));
-    }
-    if (immr->im_brgc6 != 0) {
-	printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  LRCLK\n",
-	       immr->im_brgc6,
-	       (uint)&(immr->im_brgc6),
-	       Daq_BRG_Get_Count(5),
-	       Daq_BRG_Get_ExtClk(5),
-	       Daq_BRG_Get_ExtClk_Description(5));
-    }
-    if (immr->im_brgc1 != 0) {
-	printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC1\n",
-	       immr->im_brgc1,
-	       (uint)&(immr->im_brgc1),
-	       Daq_BRG_Get_Count(0),
-	       Daq_BRG_Get_ExtClk(0),
-	       Daq_BRG_Get_ExtClk_Description(0));
-    }
-    if (immr->im_brgc2 != 0) {
-	printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC2\n",
-	       immr->im_brgc2,
-	       (uint)&(immr->im_brgc2),
-	       Daq_BRG_Get_Count(1),
-	       Daq_BRG_Get_ExtClk(1),
-	       Daq_BRG_Get_ExtClk_Description(1));
-    }
-    if (immr->im_brgc3 != 0) {
-	printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCC1\n",
-	       immr->im_brgc3,
-	       (uint)&(immr->im_brgc3),
-	       Daq_BRG_Get_Count(2),
-	       Daq_BRG_Get_ExtClk(2),
-	       Daq_BRG_Get_ExtClk_Description(2));
-    }
-    if (immr->im_brgc5 != 0) {
-	printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
-	       immr->im_brgc5,
-	       (uint)&(immr->im_brgc5),
-	       Daq_BRG_Get_Count(4),
-	       Daq_BRG_Get_ExtClk(4),
-	       Daq_BRG_Get_ExtClk_Description(4));
-    }
-    if (immr->im_brgc7 != 0) {
-	printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
-	       immr->im_brgc7,
-	       (uint)&(immr->im_brgc7),
-	       Daq_BRG_Get_Count(6),
-	       Daq_BRG_Get_ExtClk(6),
-	       Daq_BRG_Get_ExtClk_Description(6));
-    }
-
-#   ifdef RUN_SCLK_ON_BRG_INT
-	mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
-#   else
-	mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
-#   endif
-#   ifdef RUN_LRCLK_ON_BRG_INT
-	sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
-#   else
-	sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
-#   endif
-
-    printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
-    printf("\tMCLK  %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
-	   Daq_BRG_Rate(MCLK_BRG),
-	   mclk_divisor,
-	   mclk_divisor * sclk_divisor);
-#   ifdef RUN_SCLK_ON_BRG_INT
-	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
-	       Daq_BRG_Rate(SCLK_BRG),
-	       sclk_divisor);
-#   else
-	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
-	       Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
-	       sclk_divisor);
-#   endif
-#   ifdef RUN_LRCLK_ON_BRG_INT
-	printf("\tLRCLK %8d Hz\n",
-	       Daq_BRG_Rate(LRCLK_BRG));
-#   else
-#       ifdef RUN_SCLK_ON_BRG_INT
-	    printf("\tLRCLK %8d Hz\n",
-		   Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
-#       else
-	    printf("\tLRCLK %8d Hz\n",
-		   Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
-#       endif
-#   endif
-    printf("\n");
-}
diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h
deleted file mode 100644
index 3f759dd..0000000
--- a/board/sacsng/clkinit.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * (C) Copyright 2002
- * Custom IDEAS, Inc. <www.cideas.com>
- * Jon Diekema <diekema@cideas.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define SLRCLK_EN_MASK  0x00040000 /* PA13 - SLRCLK_EN*     */
-
-#define MIN_SAMPLE_RATE       4000 /* Minimum sample rate */
-#define MAX_128x_SAMPLE_RATE 43402 /* Maximum 128x sample rate */
-#define MAX_64x_SAMPLE_RATE  86805 /* Maximum  64x sample rate */
-
-#define KHZ          ((uint)1000)
-#define MHZ          ((uint)(1000 * KHZ))
-
-#define MCLK_BRG     3        /* MCLK, Master CLocK for the A/D & D/A   */
-#define SCLK_BRG     7        /* SCLK, Sample CLocK for the A/D & D/A   */
-#define LRCLK_BRG    5        /* LRCLK, L/R CLocK for the A/D & D/A     */
-			      /*   0 == BRG1 (used for SMC1)            */
-			      /*   1 == BRG2 (used for SMC2)            */
-			      /*   2 == BRG3 (used for SCC1)            */
-			      /*   3 == BRG4 (MCLK)                     */
-			      /*   4 == BRG5                            */
-			      /*   5 == BRG6 (LRCLK)                    */
-			      /*   6 == BRG7                            */
-			      /*   7 == BRG8 (SCLK)                     */
-
-#define MCLK_DIVISOR  4       /*  SCLK = MCLK / MCLK_DIVISOR */
-#define SCLK_DIVISOR (Daq64xSampling ? 64 : 128)
-			      /* LRCLK = SCLK / SCLK_DIVISOR */
-
-#define TIGHTEN_UP_BRG_EN_TIMING /* Tighten up the BRG enable timing      */
-#define RUN_SCLK_ON_BRG_INT      /* Run SCLK on BRG_INT instead of MCLK   */
-				 /* The 8260 (Mask B.3) seems to have     */
-				 /* problems generating SCLK from MCLK    */
-				 /* via CLK9.                             */
-#define RUN_LRCLK_ON_BRG_INT     /* Run LRCLK on BRG_INT instead of SCLK  */
-				 /* The 8260 (Mask B.3) seems to have     */
-				 /* problems generating LRCLK from SCLK   */
-
-#define NUM_LRCLKS_TO_STABILIZE 1  /* Number of LRCLK period (sample)     */
-				   /* to wait for the clock to stabilize  */
-
-#define CPM_CLK      (gd->bd->bi_cpmfreq)
-#define DFBRG        4
-#define BRG_INT_CLK  (CPM_CLK * 2 / DFBRG)
-			      /* BRG = CPM * 2 / DFBRG (Sect 9.8) */
-			      /* BRG = CPM * 2 / 4                */
-			      /* BRG = CPM / 2                    */
-
-#define CPM_BRG_EXTC_MASK	((uint)0x0000C000)
-#define CPM_BRG_EXTC_SHIFT      14
-
-#define CPM_BRG_DIV16_MASK	((uint)0x00000001)
-#define CPM_BRG_DIV16_SHIFT     1
-
-#define CPM_BRG_EXTC_BRGCLK     0
-#define CPM_BRG_EXTC_CLK3       1
-#define CPM_BRG_EXTC_CLK9       CPM_BRG_EXTC_CLK3
-#define CPM_BRG_EXTC_CLK5       2
-#define CPM_BRG_EXTC_CLK15      CPM_BRG_EXTC_CLK5
-
-#define IM_BRGC1 ((uint *)0xf00119f0)
-#define IM_BRGC2 ((uint *)0xf00119f4)
-#define IM_BRGC3 ((uint *)0xf00119f8)
-#define IM_BRGC4 ((uint *)0xf00119fc)
-#define IM_BRGC5 ((uint *)0xf00115f0)
-#define IM_BRGC6 ((uint *)0xf00115f4)
-#define IM_BRGC7 ((uint *)0xf00115f8)
-#define IM_BRGC8 ((uint *)0xf00115fc)
-
-/*
- * External declarations
- */
-
-extern int Daq64xSampling;
-
-extern void Daq_BRG_Reset(uint brg);
-extern void Daq_BRG_Run(uint brg);
-
-extern void Daq_BRG_Disable(uint brg);
-extern void Daq_BRG_Enable(uint brg);
-
-extern uint Daq_BRG_Get_Div16(uint brg);
-extern void Daq_BRG_Set_Div16(uint brg, uint div16);
-
-extern uint Daq_BRG_Get_Count(uint brg);
-extern void Daq_BRG_Set_Count(uint brg, uint brg_cnt);
-
-extern uint Daq_BRG_Get_ExtClk(uint brg);
-extern char* Daq_BRG_Get_ExtClk_Description(uint brg);
-extern void Daq_BRG_Set_ExtClk(uint brg, uint extc);
-
-extern uint Daq_BRG_Rate(uint brg);
-
-extern uint Daq_Get_SampleRate(void);
-
-extern void Daq_Init_Clocks(int sample_rate, int sample_64x);
-extern void Daq_Stop_Clocks(void);
-extern void Daq_Start_Clocks(int sample_rate);
-extern void Daq_Display_Clocks(void);
diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c
deleted file mode 100644
index 686fb22..0000000
--- a/board/sacsng/flash.c
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <configs/sacsng.h>
-
-
-#undef  DEBUG
-
-#ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#endif
-#ifndef CONFIG_ENV_SIZE
-#define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
-#endif
-
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_short *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0, size_b1;
-	int i;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	size_b0 = flash_get_size((vu_short *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	size_b1 = flash_get_size((vu_short *)CONFIG_SYS_FLASH1_BASE, &flash_info[1]);
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-		      &flash_info[0]);
-#endif
-
-	if (size_b1) {
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		/* monitor protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_SYS_MONITOR_BASE,
-			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-			      &flash_info[1]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-		/* ENV protection ON by default */
-		flash_protect(FLAG_PROTECT_SET,
-			      CONFIG_ENV_ADDR,
-			      CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
-			      &flash_info[1]);
-#endif
-	} else {
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-	}
-
-	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;
-
-	/*
-	 * We only report the primary flash for U-Boot's use.
-	 */
-	return (size_b0);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit, top boot sector)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-
-static ulong flash_get_size (vu_short *addr, flash_info_t *info)
-{
-	short i;
-	ushort value;
-	ulong  base = (ulong)addr;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x0555] = 0xAAAA;
-	addr[0x02AA] = 0x5555;
-	addr[0x0555] = 0x9090;
-	__asm__ __volatile__(" sync\n ");
-
-	value = addr[0];
-#ifdef DEBUG
-	printf("Flash manufacturer 0x%04X\n", value);
-#endif
-
-	if(value == (ushort)AMD_MANUFACT) {
-		info->flash_id = FLASH_MAN_AMD;
-	} else if (value == (ushort)FUJ_MANUFACT) {
-		info->flash_id = FLASH_MAN_FUJ;
-	} else {
-#ifdef DEBUG
-		printf("Unknown flash manufacturer 0x%04X\n", value);
-#endif
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-	}
-
-	value = addr[1];			/* device ID		*/
-#ifdef DEBUG
-	printf("Flash type 0x%04X\n", value);
-#endif
-
-	if(value == (ushort)AMD_ID_LV400T) {
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00080000;	/* => 0.5 MB		*/
-	} else if(value == (ushort)AMD_ID_LV400B) {
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00080000;	/* => 0.5 MB		*/
-	} else if(value == (ushort)AMD_ID_LV800T) {
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00100000;	/* => 1 MB		*/
-	} else if(value == (ushort)AMD_ID_LV800B) {
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00100000;	/* => 1 MB		*/
-	} else if(value == (ushort)AMD_ID_LV160T) {
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00200000;	/* => 2 MB		*/
-	} else if(value == (ushort)AMD_ID_LV160B) {
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00200000;	/* => 2 MB		*/
-	} else if(value == (ushort)AMD_ID_LV320T) {
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00400000;	/* => 4 MB		*/
-	} else if(value == (ushort)AMD_ID_LV320B) {
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00400000;	/* => 4 MB		*/
-	} else {
-#ifdef DEBUG
-		printf("Unknown flash type 0x%04X\n", value);
-		info->size = CONFIG_SYS_FLASH_SIZE;
-#else
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-#endif
-	}
-
-	/* set up sector start address table */
-	if (info->flash_id & FLASH_BTYPE) {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + ((i - 3) * 0x00010000);
-		}
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + (i * 0x00010000);
-		}
-	}
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile unsigned short *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile unsigned short *)info->start[0];
-
-	}
-
-	addr[0] = 0xF0F0;	/* reset bank */
-	__asm__ __volatile__(" sync\n ");
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	vu_short *addr = (vu_short*)(info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > FLASH_AMD_COMP)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	addr[0x0555] = 0xAAAA;
-	addr[0x02AA] = 0x5555;
-	addr[0x0555] = 0x8080;
-	addr[0x0555] = 0xAAAA;
-	addr[0x02AA] = 0x5555;
-	__asm__ __volatile__(" sync\n ");
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (vu_short*)(info->start[sect]);
-			addr[0] = 0x3030;
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (vu_short*)(info->start[l_sect]);
-	while ((addr[0] & 0x0080) != 0x0080) {
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			addr[0] = 0xF0F0;	/* reset bank */
-			__asm__ __volatile__(" sync\n ");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (vu_short*)info->start[0];
-	addr[0] = 0xF0F0;	/* reset bank */
-	__asm__ __volatile__(" sync\n ");
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	vu_short *addr = (vu_short*)(info->start[0]);
-	ulong start;
-	int flag;
-	int j;
-
-	/* Check if Flash is (sufficiently) erased */
-	if (((*(vu_long *)dest) & data) != data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* The original routine was designed to write 32 bit words to
-	 * 32 bit wide memory.	We have 16 bit wide memory so we do
-	 * two writes.	We write the LSB first at dest+2 and then the
-	 * MSB at dest (lousy big endian).
-	 */
-	dest += 2;
-	for(j = 0; j < 2; j++) {
-		addr[0x0555] = 0xAAAA;
-		addr[0x02AA] = 0x5555;
-		addr[0x0555] = 0xA0A0;
-		__asm__ __volatile__(" sync\n ");
-
-		*((vu_short *)dest) = (ushort)data;
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while (*(vu_short *)dest != (ushort)data) {
-			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-		dest -= 2;
-		data >>= 16;
-	}
-	return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
diff --git a/board/sacsng/ioconfig.h b/board/sacsng/ioconfig.h
deleted file mode 100644
index ac8f152..0000000
--- a/board/sacsng/ioconfig.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * I/O Port configuration table
- *
- * If conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#ifdef SKIP
-#undef SKIP
-#endif
-
-#ifdef CONF
-#undef CONF
-#endif
-
-#ifdef DIN
-#undef DIN
-#endif
-
-#ifdef DOUT
-#undef DOUT
-#endif
-
-#ifdef GPIO
-#undef GPIO
-#endif
-
-#ifdef SPEC
-#undef SPEC
-#endif
-
-#ifdef ACTV
-#undef ACTV
-#endif
-
-#ifdef OPEN
-#undef OPEN
-#endif
-
-#define SKIP 0  /* SKIP over this port */
-#define CONF 1  /* CONFiguration the port */
-
-#define DIN  0  /* PDIRx 0: Direction IN  */
-#define DOUT 1  /* PDIRx 1: Direction OUT */
-
-#define GPIO 0  /* PPARx 0: General Purpose I/O */
-#define SPEC 1  /* PPARx 1: dedicated to a peripheral function, */
-		/*          i.e. the port has a SPECial use. */
-
-#define ACTV 0  /* PODRx 0: ACTiVely driven as an output */
-#define OPEN 1  /* PODRx 1: OPEN-drain driver */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	     conf  ppar  psor  pdir  podr  pdat */
-	/* PA31 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS8*        */
-	/* PA30 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS7*        */
-	/* PA29 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS6*        */
-	/* PA28 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS5*        */
-	/* PA27 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS4*        */
-	/* PA26 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS3*        */
-	/* PA25 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS2*        */
-	/* PA24 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* RODIS1*        */
-	/* PA23 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* ODIS_EN*       */
-	/* PA22 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED2_EN*     */
-	/* PA21 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* STLED1_EN*     */
-	/* PA20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED3_EN*      */
-	/* PA19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PLED2_EN*      */
-	/* PA18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* PLED1_EN*      */
-	/* PA17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PA16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* DAC_RST*       */
-	/* PA15 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH34SDATA_PU   */
-	/* PA14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* CH12SDATA_PU   */
-	/* PA13 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SLRCLK_EN*     */
-	/* PA12 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4ACDC*    */
-	/* PA11 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4TEDS*    */
-	/* PA10 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_4XTDS*    */
-	/* PA9  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3ACDC*    */
-	/* PA8  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3TEDS*    */
-	/* PA7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_3XTDS*    */
-	/* PA6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2ACDC*    */
-	/* PA5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2TEDS*    */
-	/* PA4  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_2XTDS*    */
-	/* PA3  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PA2  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1ACDC*    */
-	/* PA1  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* MTRX_1TEDS*    */
-	/* PA0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }  /* MTRX_1XTDS*    */
-    },
-
-    /* Port B configuration */
-    {	/*	     conf  ppar  psor  pdir  podr  pdat */
-	/* PB31 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_ER */
-	/* PB30 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_DV */
-	/* PB29 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* FCC2 MII_TX_EN */
-	/* PB28 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RX_ER */
-	/* PB27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_COL   */
-	/* PB26 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_CRS   */
-	/* PB25 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD3  */
-	/* PB24 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD2  */
-	/* PB23 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD1  */
-	/* PB22 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* FCC2 MII_TXD0  */
-	/* PB21 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD0  */
-	/* PB20 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD1  */
-	/* PB19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD2  */
-	/* PB18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* FCC2 MII_RXD3  */
-	/* PB17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PB16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PB15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PB14 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDC1,   BSDATA_ADC12 */
-	/* PB13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PB12 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCC1, LRCLK  */
-	/* PB11 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1TXDD1,   RSDATA_DAC12 */
-	/* PB10 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RXDD1,   BSDATA_ADC34 */
-	/* PB9  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PB8  */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* L1RSYNCD1, LRCLK  */
-	/* PB7  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PB6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* XCITE_SHDN     */
-	/* PB5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* TRIGGER        */
-	/* PB4  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* ARM            */
-	/* PB3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
-	/* PB2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
-	/* PB1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
-	/* PB0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {	/*	      conf ppar  psor  pdir  podr  pdat */
-	/* PC31 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC30 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC29 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK3,  MCLK    */
-	/* PC28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
-#ifdef QQQ
-	/* PC28 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TOUT2*         */
-#endif
-	/* PC27 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK5,  SCLK    */
-	/* PC26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC25 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK7,  SCLK    */
-	/* PC24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC23 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK9,  MCLK    */
-	/* PC22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC21 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO6 (LRCLK)  */
-	/* PC20 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC19 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK13, MII_RXCLK  */
-	/* PC18 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* CLK14, MII_TXCLK  */
-	/* PC17 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* BRGO8 (SCLK)   */
-	/* PC16 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC15 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC2_TX        */
-	/* PC14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC13 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB3      */
-	/* PC11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* TDM_STRB4      */
-	/* PC9  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN3      */
-	/* PC8  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN2      */
-	/* PC7  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BPDIS_IN1      */
-	/* PC6  */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PC5  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN2*      */
-	/* PC4  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* BTST_IN1*      */
-	/* PC3  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* MUSH_STAT      */
-	/* PC2  */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* OUTDRV_STAT    */
-	/* PC1  */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* PHY_MDIO       */
-	/* PC0  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* PHY_MDC        */
-    },
-
-    /* Port D */
-    {	/*	      conf ppar  psor  pdir  podr  pdat */
-	/* PD31 */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SCC1_RX        */
-	/* PD30 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SCC1_TX        */
-	/* PD29 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD28 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD27 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD26 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD25 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD24 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD23 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD22 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD21 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD20 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_ADC_CS*    */
-	/* PD19 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* SPI_DAC_CS*    */
-#if defined(CONFIG_SOFT_SPI)
-	/* PD18 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_CLK        */
-	/* PD17 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
-	/* PD16 */ { CONF, GPIO,   0,  DIN,  ACTV,   0   }, /* SPI_MISO       */
-#else
-	/* PD18 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_CLK        */
-	/* PD17 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* SPI_MOSI       */
-	/* PD16 */ { CONF, SPEC,   1,  DIN,  ACTV,   0   }, /* SPI_MISO       */
-#endif
-#if defined(CONFIG_SYS_I2C_SOFT)
-	/* PD15 */ { CONF, GPIO,   0,  DOUT, OPEN,   1   }, /* I2C_SDA        */
-	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* I2C_SCL        */
-#else
-#if defined(CONFIG_HARD_I2C)
-	/* PD15 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SDA        */
-	/* PD14 */ { CONF, SPEC,   1,  DIN,  OPEN,   0   }, /* I2C_SCL        */
-#else /* normal I/O port pins */
-	/* PD15 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SDA        */
-	/* PD14 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* I2C_SCL        */
-#endif
-#endif
-	/* PD13 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB1      */
-	/* PD12 */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* TDM_STRB2      */
-	/* PD11 */ { CONF, GPIO,   0,  DOUT, ACTV,   0   }, /* N/C            */
-	/* PD10 */ { CONF, SPEC,   1,  DOUT, ACTV,   0   }, /* BRGO4 (MCLK)   */
-	/* PD9  */ { CONF, SPEC,   0,  DOUT, ACTV,   0   }, /* SMC1_TX        */
-	/* PD8  */ { CONF, SPEC,   0,  DIN,  ACTV,   0   }, /* SMC1_RX        */
-	/* PD7  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
-	/* PD6  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
-	/* PD5  */ { CONF, GPIO,   0,  DOUT, ACTV,   1   }, /* N/C            */
-	/* PD4  */ { CONF, SPEC,   1,  DOUT, ACTV,   1   }, /* SMC2_RX        */
-	/* PD3  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
-	/* PD2  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
-	/* PD1  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }, /* pin doesn't exist */
-	/* PD0  */ { SKIP, GPIO,   0,  DIN,  ACTV,   0   }  /* pin doesn't exist */
-    }
-};
diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c
deleted file mode 100644
index 91c4987..0000000
--- a/board/sacsng/sacsng.c
+++ /dev/null
@@ -1,848 +0,0 @@
-/*
- * (C) Copyright 2002
- * Custom IDEAS, Inc. <www.cideas.com>
- * Gerald Van Baren <vanbaren@cideas.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <i2c.h>
-#include <spi.h>
-#include <command.h>
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-#include <status_led.h>
-#endif
-
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
-extern void eth_loopback_test(void);
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
-#include "clkinit.h"
-#include "ioconfig.h"		/* I/O configuration table */
-
-/*
- * PBI Page Based Interleaving
- *   PSDMR_PBI page based interleaving
- *   0         bank based interleaving
- * External Address Multiplexing (EAMUX) adds a clock to address cycles
- *   (this can help with marginal board layouts)
- *   PSDMR_EAMUX  adds a clock
- *   0            no extra clock
- * Buffer Command (BUFCMD) adds a clock to command cycles.
- *   PSDMR_BUFCMD adds a clock
- *   0            no extra clock
- */
-#define CONFIG_PBI		PSDMR_PBI
-#define PESSIMISTIC_SDRAM	0
-#define EAMUX			0	/* EST requires EAMUX */
-#define BUFCMD			0
-
-/*
- * ADC/DAC Defines:
- */
-#define INITIAL_SAMPLE_RATE 10016	/* Initial Daq sample rate */
-#define INITIAL_RIGHT_JUST  0	/* Initial DAC right justification */
-#define INITIAL_MCLK_DIVIDE 0	/* Initial MCLK Divide */
-#define INITIAL_SAMPLE_64X  1	/* Initial  64x clocking mode */
-#define INITIAL_SAMPLE_128X 0	/* Initial 128x clocking mode */
-
-/*
- * ADC Defines:
- */
-#define I2C_ADC_1_ADDR 0x0E	/* I2C Address of the ADC #1 */
-#define I2C_ADC_2_ADDR 0x0F	/* I2C Address of the ADC #2 */
-
-#define ADC_SDATA1_MASK 0x00020000	/* PA14 - CH12SDATA_PU   */
-#define ADC_SDATA2_MASK 0x00010000	/* PA15 - CH34SDATA_PU   */
-
-#define ADC_VREF_CAP		100	/* VREF capacitor in uF */
-#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP)	/* 10 usec per uF, in usec */
-#define ADC_SDATA_DELAY		100	/* ADC SDATA release delay in usec */
-#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
-					/* Wait at least 4100 LRCLK's */
-
-#define ADC_REG1_FRAME_START    0x80	/* Frame start */
-#define ADC_REG1_GROUND_CAL     0x40	/* Ground calibration enable */
-#define ADC_REG1_ANA_MOD_PDOWN  0x20	/* Analog modulator section in power down */
-#define ADC_REG1_DIG_MOD_PDOWN  0x10	/* Digital modulator section in power down */
-
-#define ADC_REG2_128x           0x80	/* Oversample at 128x */
-#define ADC_REG2_CAL            0x40	/* System calibration enable */
-#define ADC_REG2_CHANGE_SIGN    0x20	/* Change sign enable */
-#define ADC_REG2_LR_DISABLE     0x10	/* Left/Right output disable */
-#define ADC_REG2_HIGH_PASS_DIS  0x08	/* High pass filter disable */
-#define ADC_REG2_SLAVE_MODE     0x04	/* Slave mode */
-#define ADC_REG2_DFS            0x02	/* Digital format select */
-#define ADC_REG2_MUTE           0x01	/* Mute */
-
-#define ADC_REG7_ADDR_ENABLE    0x80	/* Address enable */
-#define ADC_REG7_PEAK_ENABLE    0x40	/* Peak enable */
-#define ADC_REG7_PEAK_UPDATE    0x20	/* Peak update */
-#define ADC_REG7_PEAK_FORMAT    0x10	/* Peak display format */
-#define ADC_REG7_DIG_FILT_PDOWN 0x04	/* Digital filter power down enable */
-#define ADC_REG7_FIR2_IN_EN     0x02	/* External FIR2 input enable */
-#define ADC_REG7_PSYCHO_EN      0x01	/* External pyscho filter input enable */
-
-/*
- * DAC Defines:
- */
-
-#define I2C_DAC_ADDR 0x11	/* I2C Address of the DAC */
-
-#define DAC_RST_MASK 0x00008000	/* PA16 - DAC_RST*  */
-#define DAC_RESET_DELAY    100	/* DAC reset delay in usec */
-#define DAC_INITIAL_DELAY 5000	/* DAC initialization delay in usec */
-
-#define DAC_REG1_AMUTE		0x80	/* Auto-mute */
-
-#define DAC_REG1_LEFT_JUST_24_BIT (0 << 4)	/* Fmt 0: Left justified 24 bit  */
-#define DAC_REG1_I2S_24_BIT       (1 << 4)	/* Fmt 1: I2S up to 24 bit       */
-#define DAC_REG1_RIGHT_JUST_16BIT (2 << 4)	/* Fmt 2: Right justified 16 bit */
-#define DAC_REG1_RIGHT_JUST_24BIT (3 << 4)	/* Fmt 3: Right justified 24 bit */
-#define DAC_REG1_RIGHT_JUST_20BIT (4 << 4)	/* Fmt 4: Right justified 20 bit */
-#define DAC_REG1_RIGHT_JUST_18BIT (5 << 4)	/* Fmt 5: Right justified 18 bit */
-
-#define DAC_REG1_DEM_NO           (0 << 2)	/* No      De-emphasis  */
-#define DAC_REG1_DEM_44KHZ        (1 << 2)	/* 44.1KHz De-emphasis  */
-#define DAC_REG1_DEM_48KHZ        (2 << 2)	/* 48KHz   De-emphasis  */
-#define DAC_REG1_DEM_32KHZ        (3 << 2)	/* 32KHz   De-emphasis  */
-
-#define DAC_REG1_SINGLE 0	/*   4- 50KHz sample rate  */
-#define DAC_REG1_DOUBLE 1	/*  50-100KHz sample rate  */
-#define DAC_REG1_QUAD   2	/* 100-200KHz sample rate  */
-#define DAC_REG1_DSD    3	/* Direct Stream Data, DSD */
-
-#define DAC_REG5_INVERT_A   0x80	/* Invert channel A */
-#define DAC_REG5_INVERT_B   0x40	/* Invert channel B */
-#define DAC_REG5_I2C_MODE   0x20	/* Control port (I2C) mode */
-#define DAC_REG5_POWER_DOWN 0x10	/* Power down mode */
-#define DAC_REG5_MUTEC_A_B  0x08	/* Mutec A=B */
-#define DAC_REG5_FREEZE     0x04	/* Freeze */
-#define DAC_REG5_MCLK_DIV   0x02	/* MCLK divide by 2 */
-#define DAC_REG5_RESERVED   0x01	/* Reserved */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard(void)
-{
-	printf("SACSng\n");
-
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar c = 0;
-	volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
-	uint psdmr = CONFIG_SYS_PSDMR;
-	int i;
-	uint psrt = 14;		/* for no SPD */
-	uint chipselects = 1;	/* for no SPD */
-	uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024;	/* for no SPD */
-	uint or = CONFIG_SYS_OR2_PRELIM;	/* for no SPD */
-
-#ifdef SDRAM_SPD_ADDR
-	uint data_width;
-	uint rows;
-	uint banks;
-	uint cols;
-	uint caslatency;
-	uint width;
-	uint rowst;
-	uint sdam;
-	uint bsma;
-	uint sda10;
-	u_char data;
-	u_char cksum;
-	int j;
-#endif
-
-#ifdef SDRAM_SPD_ADDR
-	/* Keep the compiler from complaining about potentially uninitialized vars */
-	data_width = chipselects = rows = banks = cols = caslatency = psrt =
-		0;
-
-	/*
-	 * Read the SDRAM SPD EEPROM via I2C.
-	 */
-	i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
-	cksum = data;
-	for (j = 1; j < 64; j++) {	/* read only the checksummed bytes */
-		/* note: the I2C address autoincrements when alen == 0 */
-		i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
-		if (j == 5)
-			chipselects = data & 0x0F;
-		else if (j == 6)
-			data_width = data;
-		else if (j == 7)
-			data_width |= data << 8;
-		else if (j == 3)
-			rows = data & 0x0F;
-		else if (j == 4)
-			cols = data & 0x0F;
-		else if (j == 12) {
-			/*
-			 * Refresh rate: this assumes the prescaler is set to
-			 * approximately 1uSec per tick.
-			 */
-			switch (data & 0x7F) {
-			default:
-			case 0:
-				psrt = 14;	/*  15.625uS */
-				break;
-			case 1:
-				psrt = 2;	/*   3.9uS   */
-				break;
-			case 2:
-				psrt = 6;	/*   7.8uS   */
-				break;
-			case 3:
-				psrt = 29;	/*  31.3uS   */
-				break;
-			case 4:
-				psrt = 60;	/*  62.5uS   */
-				break;
-			case 5:
-				psrt = 120;	/* 125uS     */
-				break;
-			}
-		} else if (j == 17)
-			banks = data;
-		else if (j == 18) {
-			caslatency = 3;	/* default CL */
-#if(PESSIMISTIC_SDRAM)
-			if ((data & 0x04) != 0)
-				caslatency = 3;
-			else if ((data & 0x02) != 0)
-				caslatency = 2;
-			else if ((data & 0x01) != 0)
-				caslatency = 1;
-#else
-			if ((data & 0x01) != 0)
-				caslatency = 1;
-			else if ((data & 0x02) != 0)
-				caslatency = 2;
-			else if ((data & 0x04) != 0)
-				caslatency = 3;
-#endif
-			else {
-				printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data);
-			}
-		} else if (j == 63) {
-			if (data != cksum) {
-				printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum);
-			}
-		}
-		cksum += data;
-	}
-
-	/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
-	if (caslatency < 2) {
-		printf("WARNING: CL was %d, forcing to 2\n", caslatency);
-		caslatency = 2;
-	}
-	if (rows > 14) {
-		printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n",
-			rows);
-		rows = 14;
-	}
-	if (cols > 11) {
-		printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n",
-			cols);
-		cols = 11;
-	}
-
-	if ((data_width != 64) && (data_width != 72)) {
-		printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
-			data_width);
-	}
-	width = 3;		/* 2^3 = 8 bytes = 64 bits wide */
-	/*
-	 * Convert banks into log2(banks)
-	 */
-	if (banks == 2)
-		banks = 1;
-	else if (banks == 4)
-		banks = 2;
-	else if (banks == 8)
-		banks = 3;
-
-	sdram_size = 1 << (rows + cols + banks + width);
-
-#if(CONFIG_PBI == 0)		/* bank-based interleaving */
-	rowst = ((32 - 6) - (rows + cols + width)) * 2;
-#else
-	rowst = 32 - (rows + banks + cols + width);
-#endif
-
-	or = ~(sdram_size - 1) |	/* SDAM address mask    */
-		((banks - 1) << 13) |	/* banks per device     */
-		(rowst << 9) |		/* rowst                */
-		((rows - 9) << 6);	/* numr                 */
-
-	memctl->memc_or2 = or;
-
-	/*
-	 * SDAM specifies the number of columns that are multiplexed
-	 * (reference AN2165/D), defined to be (columns - 6) for page
-	 * interleave, (columns - 8) for bank interleave.
-	 *
-	 * BSMA is 14 - max(rows, cols).  The bank select lines come
-	 * into play above the highest "address" line going into the
-	 * the SDRAM.
-	 */
-#if(CONFIG_PBI == 0)		/* bank-based interleaving */
-	sdam = cols - 8;
-	bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
-	sda10 = sdam + 2;
-#else
-	sdam = cols - 6;
-	bsma = ((31 - width) - 14) - ((rows > cols) ? rows : cols);
-	sda10 = sdam;
-#endif
-#if(PESSIMISTIC_SDRAM)
-	psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
-		PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
-		PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
-		((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */
-		(sdam << 24) | (bsma << 21) | (sda10 << 18);
-#else
-	psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
-		PSDMR_PRETOACT_3W |	/* 1 for 7E parts (fast PC-133) */
-		PSDMR_ACTTORW_2W |	/* 1 for 7E parts (fast PC-133) */
-		PSDMR_WRC_1C |	/* 1 clock + 7nSec */
-		EAMUX | BUFCMD) |
-		caslatency | ((caslatency - 1) << 6) |	/* LDOTOPRE is CL - 1 */
-		(sdam << 24) | (bsma << 21) | (sda10 << 18);
-#endif
-#endif
-
-	/*
-	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
-	 *
-	 * "At system reset, initialization software must set up the
-	 *  programmable parameters in the memory controller banks registers
-	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
-	 *  system software should execute the following initialization sequence
-	 *  for each SDRAM device.
-	 *
-	 *  1. Issue a PRECHARGE-ALL-BANKS command
-	 *  2. Issue eight CBR REFRESH commands
-	 *  3. Issue a MODE-SET command to initialize the mode register
-	 *
-	 * Quote from Micron MT48LC8M16A2 data sheet:
-	 *
-	 *  "...the SDRAM requires a 100uS delay prior to issuing any
-	 *  command other than a COMMAND INHIBIT or NOP.  Starting at some
-	 *  point during this 100uS period and continuing at least through
-	 *  the end of this period, COMMAND INHIBIT or NOP commands should
-	 *  be applied."
-	 *
-	 *  "Once the 100uS delay has been satisfied with at least one COMMAND
-	 *  INHIBIT or NOP command having been applied, a /PRECHARGE command/
-	 *  should be applied.  All banks must then be precharged, thereby
-	 *  placing the device in the all banks idle state."
-	 *
-	 *  "Once in the idle state, /two/ AUTO REFRESH cycles must be
-	 *  performed.  After the AUTO REFRESH cycles are complete, the
-	 *  SDRAM is ready for mode register programming."
-	 *
-	 *  (/emphasis/ mine, gvb)
-	 *
-	 *  The way I interpret this, Micron start up sequence is:
-	 *  1. Issue a PRECHARGE-BANK command (initial precharge)
-	 *  2. Issue a PRECHARGE-ALL-BANKS command ("all banks ... precharged")
-	 *  3. Issue two (presumably, doing eight is OK) CBR REFRESH commands
-	 *  4. Issue a MODE-SET command to initialize the mode register
-	 *
-	 *  --------
-	 *
-	 *  The initial commands are executed by setting P/LSDMR[OP] and
-	 *  accessing the SDRAM with a single-byte transaction."
-	 *
-	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
-	 */
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-	memctl->memc_psrt = psrt;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
-	*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
-	*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-	*ramaddr = c;
-
-	/*
-	 * Do it a second time for the second set of chips if the DIMM has
-	 * two chip selects (double sided).
-	 */
-	if (chipselects > 1) {
-		ramaddr += sdram_size;
-
-		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
-		memctl->memc_or3 = or;
-
-		memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
-		*ramaddr = c;
-
-		memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
-		for (i = 0; i < 8; i++)
-			*ramaddr = c;
-
-		memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
-		*ramaddr = c;
-
-		memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
-		*ramaddr = c;
-	}
-
-	/* return total ram size */
-	return (sdram_size * chipselects);
-}
-
-/*-----------------------------------------------------------------------
- * Board Control Functions
- */
-void board_poweroff(void)
-{
-	while (1);		/* hang forever */
-}
-
-
-#ifdef CONFIG_MISC_INIT_R
-/* ------------------------------------------------------------------------- */
-int misc_init_r(void)
-{
-	/*
-	 * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
-	 */
-	volatile ioport_t *iopa =
-		ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ );
-	volatile ioport_t *iop =
-		ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
-
-	int reg;		/* I2C register value */
-	char *ep;		/* Environment pointer */
-	char str_buf[12];	/* sprintf output buffer */
-	int sample_rate;	/* ADC/DAC sample rate */
-	int sample_64x;		/* Use  64/4 clocking for the ADC/DAC */
-	int sample_128x;	/* Use 128/4 clocking for the ADC/DAC */
-	int right_just;		/* Is the data to the DAC right justified? */
-	int mclk_divide;	/* MCLK Divide */
-	int quiet;		/* Quiet or minimal output mode */
-
-	quiet = 0;
-
-	if ((ep = getenv("quiet")) != NULL)
-		quiet = simple_strtol(ep, NULL, 10);
-	else
-		setenv("quiet", "0");
-
-	/*
-	 * SACSng custom initialization:
-	 *    Start the ADC and DAC clocks, since the Crystal parts do not
-	 *    work on the I2C bus until the clocks are running.
-	 */
-
-	sample_rate = INITIAL_SAMPLE_RATE;
-	if ((ep = getenv("DaqSampleRate")) != NULL)
-		sample_rate = simple_strtol(ep, NULL, 10);
-
-	sample_64x = INITIAL_SAMPLE_64X;
-	sample_128x = INITIAL_SAMPLE_128X;
-	if ((ep = getenv("Daq64xSampling")) != NULL) {
-		sample_64x = simple_strtol(ep, NULL, 10);
-		if (sample_64x)
-			sample_128x = 0;
-		else
-			sample_128x = 1;
-	} else {
-		if ((ep = getenv("Daq128xSampling")) != NULL) {
-			sample_128x = simple_strtol(ep, NULL, 10);
-			if (sample_128x)
-				sample_64x = 0;
-			else
-				sample_64x = 1;
-		}
-	}
-
-	/*
-	 * Stop the clocks and wait for at least 1 LRCLK period
-	 * to make sure the clocking has really stopped.
-	 */
-	Daq_Stop_Clocks();
-	udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
-
-	/*
-	 * Initialize the clocks with the new rates
-	 */
-	Daq_Init_Clocks(sample_rate, sample_64x);
-	sample_rate = Daq_Get_SampleRate();
-
-	/*
-	 * Start the clocks and wait for at least 1 LRCLK period
-	 * to make sure the clocking has become stable.
-	 */
-	Daq_Start_Clocks(sample_rate);
-	udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
-
-	sprintf(str_buf, "%d", sample_rate);
-	setenv("DaqSampleRate", str_buf);
-
-	if (sample_64x) {
-		setenv("Daq64xSampling", "1");
-		setenv("Daq128xSampling", NULL);
-	} else {
-		setenv("Daq64xSampling", NULL);
-		setenv("Daq128xSampling", "1");
-	}
-
-	/*
-	 * Display the ADC/DAC clocking information
-	 */
-	if (!quiet)
-		Daq_Display_Clocks();
-
-	/*
-	 * Determine the DAC data justification
-	 */
-
-	right_just = INITIAL_RIGHT_JUST;
-	if ((ep = getenv("DaqDACRightJustified")) != NULL)
-		right_just = simple_strtol(ep, NULL, 10);
-
-	sprintf(str_buf, "%d", right_just);
-	setenv("DaqDACRightJustified", str_buf);
-
-	/*
-	 * Determine the DAC MCLK Divide
-	 */
-
-	mclk_divide = INITIAL_MCLK_DIVIDE;
-	if ((ep = getenv("DaqDACMClockDivide")) != NULL)
-		mclk_divide = simple_strtol(ep, NULL, 10);
-
-	sprintf(str_buf, "%d", mclk_divide);
-	setenv("DaqDACMClockDivide", str_buf);
-
-	/*
-	 * Initializing the I2C address in the Crystal A/Ds:
-	 *
-	 * 1) Wait for VREF cap to settle (10uSec per uF)
-	 * 2) Release pullup on SDATA
-	 * 3) Write the I2C address to register 6
-	 * 4) Enable address matching by setting the MSB in register 7
-	 */
-
-	if (!quiet)
-		printf("Initializing the ADC...\n");
-
-	udelay(ADC_INITIAL_DELAY);	/* 10uSec per uF of VREF cap */
-
-	iopa->pdat &= ~ADC_SDATA1_MASK;	/* release SDATA1 */
-	udelay(ADC_SDATA_DELAY);	/* arbitrary settling time */
-
-	i2c_reg_write(0x00, 0x06, I2C_ADC_1_ADDR);	/* set address */
-	i2c_reg_write(I2C_ADC_1_ADDR, 0x07,	/* turn on ADDREN */
-		      ADC_REG7_ADDR_ENABLE);
-
-	i2c_reg_write(I2C_ADC_1_ADDR, 0x02,	/* 128x, slave mode, !HPEN */
-		      (sample_64x ? 0 : ADC_REG2_128x) |
-		      ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
-
-	reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
-	if (reg != I2C_ADC_1_ADDR) {
-		printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
-			reg, I2C_ADC_1_ADDR);
-	}
-
-	iopa->pdat &= ~ADC_SDATA2_MASK;	/* release SDATA2 */
-	udelay(ADC_SDATA_DELAY);	/* arbitrary settling time */
-
-	/* set address (do not set ADDREN yet) */
-	i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);
-
-	i2c_reg_write(I2C_ADC_2_ADDR, 0x02,	/* 64x, slave mode, !HPEN */
-		      (sample_64x ? 0 : ADC_REG2_128x) |
-		      ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
-
-	reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
-	if (reg != I2C_ADC_2_ADDR) {
-		printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
-			reg, I2C_ADC_2_ADDR);
-	}
-
-	i2c_reg_write(I2C_ADC_1_ADDR, 0x01,	/* set FSTART and GNDCAL */
-		      ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL);
-
-	i2c_reg_write(I2C_ADC_1_ADDR, 0x02,	/* Start calibration */
-		      (sample_64x ? 0 : ADC_REG2_128x) |
-		      ADC_REG2_CAL |
-		      ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
-
-	udelay(ADC_CAL_DELAY);	/* a minimum of 4100 LRCLKs */
-	i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00);	/* remove GNDCAL */
-
-	/*
-	 * Now that we have synchronized the ADC's, enable address
-	 * selection on the second ADC as well as the first.
-	 */
-	i2c_reg_write(I2C_ADC_2_ADDR, 0x07, ADC_REG7_ADDR_ENABLE);
-
-	/*
-	 * Initialize the Crystal DAC
-	 *
-	 * Two of the config lines are used for I2C so we have to set them
-	 * to the proper initialization state without inadvertantly
-	 * sending an I2C "start" sequence.  When we bring the I2C back to
-	 * the normal state, we send an I2C "stop" sequence.
-	 */
-	if (!quiet)
-		printf("Initializing the DAC...\n");
-
-	/*
-	 * Bring the I2C clock and data lines low for initialization
-	 */
-	I2C_SCL(0);
-	I2C_DELAY;
-	I2C_SDA(0);
-	I2C_ACTIVE;
-	I2C_DELAY;
-
-	/* Reset the DAC */
-	iopa->pdat &= ~DAC_RST_MASK;
-	udelay(DAC_RESET_DELAY);
-
-	/* Release the DAC reset */
-	iopa->pdat |= DAC_RST_MASK;
-	udelay(DAC_INITIAL_DELAY);
-
-	/*
-	 * Cause the DAC to:
-	 *     Enable control port (I2C mode)
-	 *     Going into power down
-	 */
-	i2c_reg_write(I2C_DAC_ADDR, 0x05,
-		      DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN);
-
-	/*
-	 * Cause the DAC to:
-	 *     Enable control port (I2C mode)
-	 *     Going into power down
-	 *         . MCLK divide by 1
-	 *         . MCLK divide by 2
-	 */
-	i2c_reg_write(I2C_DAC_ADDR, 0x05,
-		      DAC_REG5_I2C_MODE |
-		      DAC_REG5_POWER_DOWN |
-		      (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
-
-	/*
-	 * Cause the DAC to:
-	 *     Auto-mute disabled
-	 *         . Format 0, left  justified 24 bits
-	 *         . Format 3, right justified 24 bits
-	 *     No de-emphasis
-	 *         . Single speed mode
-	 *         . Double speed mode
-	 */
-	i2c_reg_write(I2C_DAC_ADDR, 0x01,
-		      (right_just ? DAC_REG1_RIGHT_JUST_24BIT :
-		       DAC_REG1_LEFT_JUST_24_BIT) |
-		      DAC_REG1_DEM_NO |
-		      (sample_rate >=
-		       50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
-
-	sprintf(str_buf, "%d",
-		sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
-	setenv("DaqDACFunctionalMode", str_buf);
-
-	/*
-	 * Cause the DAC to:
-	 *     Enable control port (I2C mode)
-	 *     Remove power down
-	 *         . MCLK divide by 1
-	 *         . MCLK divide by 2
-	 */
-	i2c_reg_write(I2C_DAC_ADDR, 0x05,
-		      DAC_REG5_I2C_MODE |
-		      (mclk_divide ? DAC_REG5_MCLK_DIV : 0));
-
-	/*
-	 * Create a I2C stop condition:
-	 *     low->high on data while clock is high.
-	 */
-	I2C_SCL(1);
-	I2C_DELAY;
-	I2C_SDA(1);
-	I2C_DELAY;
-	I2C_TRISTATE;
-
-	if (!quiet)
-		printf("\n");
-#ifdef CONFIG_ETHER_LOOPBACK_TEST
-	/*
-	 * Run the Ethernet loopback test
-	 */
-	eth_loopback_test();
-#endif /* CONFIG_ETHER_LOOPBACK_TEST */
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-	/*
-	 * Turn off the RED fail LED now that we are up and running.
-	 */
-	status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-/*
- * Show boot status: flash the LED if something goes wrong, indicating
- * that last thing that worked and thus, by implication, what is broken.
- *
- * This stores the last OK value in RAM so this will not work properly
- * before RAM is initialized.  Since it is being used for indicating
- * boot status (i.e. after RAM is initialized), that is OK.
- */
-static void flash_code(uchar number, uchar modulo, uchar digits)
-{
-	int j;
-
-	/*
-	 * Recursively do upper digits.
-	 */
-	if (digits > 1)
-		flash_code(number / modulo, modulo, digits - 1);
-
-	number = number % modulo;
-
-	/*
-	 * Zero is indicated by one long flash (dash).
-	 */
-	if (number == 0) {
-		status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
-		udelay(1000000);
-		status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
-		udelay(200000);
-	} else {
-		/*
-		 * Non-zero is indicated by short flashes, one per count.
-		 */
-		for (j = 0; j < number; j++) {
-			status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
-			udelay(100000);
-			status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
-			udelay(200000);
-		}
-	}
-	/*
-	 * Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
-	 */
-	udelay(700000);
-}
-
-static int last_boot_progress;
-
-void show_boot_progress(int status)
-{
-	int i, j;
-
-	if (status > 0) {
-		last_boot_progress = status;
-	} else {
-		/*
-		 * If a specific failure code is given, flash this code
-		 * else just use the last success code we've seen
-		 */
-		if (status < -1)
-			last_boot_progress = -status;
-
-		/*
-		 * Flash this code 5 times
-		 */
-		for (j = 0; j < 5; j++) {
-			/*
-			 * Houston, we have a problem.
-			 * Blink the last OK status which indicates where things failed.
-			 */
-			status_led_set(STATUS_LED_RED, STATUS_LED_ON);
-			flash_code(last_boot_progress, 5, 3);
-
-			/*
-			 * Delay 5 seconds between repetitions,
-			 * with the fault LED blinking
-			 */
-			for (i = 0; i < 5; i++) {
-				status_led_set(STATUS_LED_RED,
-					       STATUS_LED_OFF);
-				udelay(500000);
-				status_led_set(STATUS_LED_RED, STATUS_LED_ON);
-				udelay(500000);
-			}
-		}
-
-		/*
-		 * Reset the board to retry initialization.
-		 */
-		do_reset(NULL, 0, 0, NULL);
-	}
-}
-#endif /* CONFIG_SHOW_BOOT_PROGRESS */
-
-
-/*
- * The following are used to control the SPI chip selects for the SPI command.
- */
-#if defined(CONFIG_CMD_SPI)
-
-#define SPI_ADC_CS_MASK	0x00000800
-#define SPI_DAC_CS_MASK	0x00001000
-
-static const u32 cs_mask[] = {
-	SPI_ADC_CS_MASK,
-	SPI_DAC_CS_MASK,
-};
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
-	return bus == 0 && cs < sizeof(cs_mask) / sizeof(cs_mask[0]);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
-	volatile ioport_t *iopd =
-		ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
-
-	iopd->pdat &= ~cs_mask[slave->cs];
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
-	volatile ioport_t *iopd =
-		ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
-
-	iopd->pdat |= cs_mask[slave->cs];
-}
-
-#endif
-
-#endif /* CONFIG_MISC_INIT_R */
diff --git a/boards.cfg b/boards.cfg
index bdc3784..facc240 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1160,7 +1160,6 @@ Orphan  m68k        mcf52x2        -           freescale       m5253evbe
 Orphan  powerpc     mpc5xxx        -           -               galaxy5200          galaxy5200                            galaxy5200:galaxy5200                                                                                                             Eric Millbrandt <emillbrandt@dekaresearch.com>
 Orphan  powerpc     mpc5xxx        -           -               galaxy5200          galaxy5200_LOWBOOT                    galaxy5200:galaxy5200_LOWBOOT                                                                                                     Eric Millbrandt <emillbrandt@dekaresearch.com>
 Orphan  powerpc     mpc8260        -           -               ep8260              ep8260                                -                                                                                                                                 Frank Panno <fpanno@delphintech.com>
-Orphan  powerpc     mpc8260        -           -               sacsng              sacsng                                -                                                                                                                                 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 Orphan  powerpc     mpc83xx        -           freescale       mpc837xerdb         MPC837XERDB                           -                                                                                                                                 Joe D'Abbraccio <ljd015@freescale.com>
 Orphan  powerpc     mpc85xx        -           exmeritus       hww1u1a             HWW1U1A                               -                                                                                                                                 Kyle Moffett <Kyle.D.Moffett@boeing.com>
 Orphan  powerpc     mpc85xx        -           freescale       mpc8540ads          MPC8540ADS                            -                                                                                                                                 Kumar Gala <kumar.gala@freescale.com>
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index be730f2..664c95c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+sacsng           powerpc     mpc8260        -           -           Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 flagadm          powerpc     mpc8xx         -           -           Kári Davíðsson <kd@flaga.is>
 gen860t          powerpc     mpc8xx         -           -           Keith Outwater <Keith_Outwater@mvis.com>
 sixnet           powerpc     mpc8xx         -           -           Dave Ellis <DGE@sixnetio.com>
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
deleted file mode 100644
index b5064ab..0000000
--- a/include/configs/sacsng.h
+++ /dev/null
@@ -1,1039 +0,0 @@
-/*
- * (C) Copyright 2000
- * Murray Jensen <Murray.Jensen@cmst.csiro.au>
- *
- * (C) Copyright 2000
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2001
- * Advent Networks, Inc. <http://www.adventnetworks.com>
- * Jay Monkman <jtm@smoothsmoothie.com>
- *
- * Configuration settings for the SACSng 8260 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define	CONFIG_SYS_TEXT_BASE	0x40000000
-
-#undef DEBUG_BOOTP_EXT	      /* Debug received vendor fields */
-
-#undef CONFIG_LOGBUFFER       /* External logbuffer support */
-
-/*****************************************************************************
- *
- * These settings must match the way _your_ board is set up
- *
- *****************************************************************************/
-
-/* What is the oscillator's (UX2) frequency in Hz? */
-#define CONFIG_8260_CLKIN  66666600
-
-/*-----------------------------------------------------------------------
- * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
- *-----------------------------------------------------------------------
- * What should MODCK_H be? It is dependent on the oscillator
- * frequency, MODCK[1-3], and desired CPM and core frequencies.
- * Here are some example values (all frequencies are in MHz):
- *
- * MODCK_H   MODCK[1-3]	 Osc	CPM    Core  S2-6   S2-7   S2-8
- * -------   ----------	 ---	---    ----  -----  -----  -----
- * 0x1	     0x5	 33	100    133   Open   Close  Open
- * 0x1	     0x6	 33	100    166   Open   Open   Close
- * 0x1	     0x7	 33	100    200   Open   Open   Open
- *
- * 0x2	     0x2	 33	133    133   Close  Open   Close
- * 0x2	     0x3	 33	133    166   Close  Open   Open
- * 0x2	     0x4	 33	133    200   Open   Close  Close
- * 0x2	     0x5	 33	133    233   Open   Close  Open
- * 0x2	     0x6	 33	133    266   Open   Open   Close
- *
- * 0x5	     0x5	 66	133    133   Open   Close  Open
- * 0x5	     0x6	 66	133    166   Open   Open   Close
- * 0x5	     0x7	 66	133    200   Open   Open   Open
- * 0x6	     0x0	 66	133    233   Close  Close  Close
- * 0x6	     0x1	 66	133    266   Close  Close  Open
- * 0x6	     0x2	 66	133    300   Close  Open   Close
- */
-#define CONFIG_SYS_SBC_MODCK_H 0x05
-
-/* Define this if you want to boot from 0x00000100. If you don't define
- * this, you will need to program the bootloader to 0xfff00000, and
- * get the hardware reset config words at 0xfe000000. The simplest
- * way to do that is to program the bootloader at both addresses.
- * It is suggested that you just let U-Boot live at 0x00000000.
- */
-#define CONFIG_SYS_SBC_BOOT_LOW 1
-
-/* What should the base address of the main FLASH be and how big is
- * it (in MBytes)?  This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
- * The main FLASH is whichever is connected to *CS0.
- */
-#define CONFIG_SYS_FLASH0_BASE 0x40000000
-#define CONFIG_SYS_FLASH0_SIZE 2
-
-/* What should the base address of the secondary FLASH be and how big
- * is it (in Mbytes)?  The secondary FLASH is whichever is connected
- * to *CS6.
- */
-#define CONFIG_SYS_FLASH1_BASE 0x60000000
-#define CONFIG_SYS_FLASH1_SIZE 2
-
-/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
- */
-#define CONFIG_VERY_BIG_RAM	1
-
-/* What should be the base address of SDRAM DIMM and how big is
- * it (in Mbytes)?  This will normally auto-configure via the SPD.
-*/
-#define CONFIG_SYS_SDRAM0_BASE 0x00000000
-#define CONFIG_SYS_SDRAM0_SIZE 64
-
-/*
- * Memory map example with 64 MB DIMM:
- *
- *     0x0000 0000     Exception Vector code, 8k
- *	     :
- *     0x0000 1FFF
- *     0x0000 2000     Free for Application Use
- *	     :
- *	     :
- *
- *	     :
- *	     :
- *     0x03F5 FF30     Monitor Stack (Growing downward)
- *		       Monitor Stack Buffer (0x80)
- *     0x03F5 FFB0     Board Info Data
- *     0x03F6 0000     Malloc Arena
- *	     :		    CONFIG_ENV_SECT_SIZE, 16k
- *	     :		    CONFIG_SYS_MALLOC_LEN,    128k
- *     0x03FC 0000     RAM Copy of Monitor Code
- *	     :		    CONFIG_SYS_MONITOR_LEN,   256k
- *     0x03FF FFFF     [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
- */
-
-#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | \
-				 CONFIG_SYS_POST_CPU)
-
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere.
- */
-#define CONFIG_CONS_ON_SMC	1	/* define if console on SMC */
-#undef	CONFIG_CONS_ON_SCC		/* define if console on SCC */
-#undef	CONFIG_CONS_NONE		/* define if console on neither */
-#define CONFIG_CONS_INDEX	1	/* which SMC/SCC channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-
-#undef	CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_ON_FCC
-#undef	CONFIG_ETHER_NONE		/* define if ethernet on neither */
-
-#ifdef	CONFIG_ETHER_ON_SCC
-#define CONFIG_ETHER_INDEX	1	/* which SCC/FCC channel for ethernet */
-#endif	/* CONFIG_ETHER_ON_SCC */
-
-#ifdef	CONFIG_ETHER_ON_FCC
-#define CONFIG_ETHER_INDEX	2	/* which SCC/FCC channel for ethernet */
-#undef  CONFIG_ETHER_LOOPBACK_TEST      /* Ethernet external loopback test */
-#define CONFIG_MII			/* MII PHY management		*/
-#define CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/
-/*
- * Port pins used for bit-banged MII communictions (if applicable).
- */
-
-#define MDIO_PORT	2	        /* Port A=0, B=1, C=2, D=3 */
-#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
-				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE	MDIO_DECLARE
-
-#define MDIO_ACTIVE	(iop->pdir |=  0x40000000)
-#define MDIO_TRISTATE	(iop->pdir &= ~0x40000000)
-#define MDIO_READ	((iop->pdat &  0x40000000) != 0)
-
-#define MDIO(bit)	if(bit) iop->pdat |=  0x40000000; \
-			else	iop->pdat &= ~0x40000000
-
-#define MDC(bit)	if(bit) iop->pdat |=  0x80000000; \
-			else	iop->pdat &= ~0x80000000
-
-#define MIIDELAY	udelay(50)
-#endif	/* CONFIG_ETHER_ON_FCC */
-
-#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
-
-/*
- *  - RX clk is CLK11
- *  - TX clk is CLK12
- */
-# define CONFIG_SYS_CMXSCR_VALUE1	(CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
-
-#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-
-/*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Enable Full Duplex in FSMR
- */
-# define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE	0
-# define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1	/* boot progress enabled	*/
-
-/*
- * Configure for RAM tests.
- */
-#undef  CONFIG_SYS_DRAM_TEST			/* calls other tests in board.c	*/
-
-
-/*
- * Status LED for power up status feedback.
- */
-#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
-
-#define STATUS_LED_PAR		im_ioport.iop_ppara
-#define STATUS_LED_DIR		im_ioport.iop_pdira
-#define STATUS_LED_ODR		im_ioport.iop_podra
-#define STATUS_LED_DAT		im_ioport.iop_pdata
-
-#define STATUS_LED_BIT		0x00000800	/* LED 0 is on PA.20	*/
-#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ)
-#define STATUS_LED_STATE	STATUS_LED_OFF
-#define STATUS_LED_BIT1		0x00001000	/* LED 1 is on PA.19	*/
-#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ)
-#define STATUS_LED_STATE1	STATUS_LED_OFF
-#define STATUS_LED_BIT2		0x00002000	/* LED 2 is on PA.18	*/
-#define STATUS_LED_PERIOD2	(CONFIG_SYS_HZ/2)
-#define STATUS_LED_STATE2	STATUS_LED_ON
-
-#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
-
-#define STATUS_LED_YELLOW	0
-#define STATUS_LED_GREEN	1
-#define STATUS_LED_RED		2
-#define STATUS_LED_BOOT		1
-
-
-/*
- * Select SPI support configuration
- */
-#define CONFIG_SOFT_SPI		/* Enable SPI driver */
-#define MAX_SPI_BYTES   4	/* Maximum number of bytes we can handle */
-#undef  DEBUG_SPI               /* Disable SPI debugging */
-
-/*
- * Software (bit-bang) SPI driver configuration
- */
-#ifdef CONFIG_SOFT_SPI
-
-/*
- * Software (bit-bang) SPI driver configuration
- */
-#define I2C_SCLK	0x00002000      /* PD 18: Shift clock */
-#define I2C_MOSI	0x00004000      /* PD 17: Master Out, Slave In */
-#define I2C_MISO	0x00008000      /* PD 16: Master In, Slave Out */
-
-#undef  SPI_INIT			/* no port initialization needed */
-#define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
-#define SPI_SDA(bit)    do {						\
-			if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
-			else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI;	\
-			} while (0)
-#define SPI_SCL(bit)    do {						\
-			if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
-			else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK;	\
-			} while (0)
-#define SPI_DELAY                       /* No delay is needed */
-#endif /* CONFIG_SOFT_SPI */
-
-
-/*
- * select I2C support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
-#define CONFIG_SYS_I2C_SOFT_SPEED	400000
-#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_PORT	3		/* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE	(iop->pdir |=  0x00010000)
-#define I2C_TRISTATE	(iop->pdir &= ~0x00010000)
-#define I2C_READ	((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit)	if(bit) iop->pdat |=  0x00010000; \
-			else    iop->pdat &= ~0x00010000
-#define I2C_SCL(bit)	if(bit) iop->pdat |=  0x00020000; \
-			else    iop->pdat &= ~0x00020000
-#define I2C_DELAY	udelay(20)	/* 1/4 I2C clock duration */
-
-/* Define this to reserve an entire FLASH sector for
- * environment variables. Otherwise, the environment will be
- * put in the same sector as U-Boot, and changing variables
- * will erase U-Boot temporarily
- */
-#define CONFIG_ENV_IN_OWN_SECT	1
-
-/* Define this to contain any number of null terminated strings that
- * will be part of the default environment compiled into the boot image.
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"quiet=0\0" \
-"serverip=192.168.123.205\0" \
-"ipaddr=192.168.123.203\0" \
-"checkhostname=VR8500\0" \
-"reprog="\
-    "bootp; " \
-    "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
-    "protect off 60000000 6003FFFF; " \
-    "erase 60000000 6003FFFF; " \
-    "cp.b 140000 60000000 ${filesize}; " \
-    "protect on 60000000 6003FFFF\0" \
-"copyenv="\
-    "protect off 60040000 6004FFFF; " \
-    "erase 60040000 6004FFFF; " \
-    "cp.b 40040000 60040000 10000; " \
-    "protect on 60040000 6004FFFF\0" \
-"copyprog="\
-    "protect off 60000000 6003FFFF; " \
-    "erase 60000000 6003FFFF; " \
-    "cp.b 40000000 60000000 40000; " \
-    "protect on 60000000 6003FFFF\0" \
-"zapenv="\
-    "protect off 40040000 4004FFFF; " \
-    "erase 40040000 4004FFFF; " \
-    "protect on 40040000 4004FFFF\0" \
-"zapotherenv="\
-    "protect off 60040000 6004FFFF; " \
-    "erase 60040000 6004FFFF; " \
-    "protect on 60040000 6004FFFF\0" \
-"root-on-initrd="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/ram0 rw quiet " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"root-on-initrd-debug="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/ram0 rw debug " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run debug-hook\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"root-on-nfs="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/nfs rw quiet " \
-    "nfsroot=\\${serverip}:\\${rootpath} " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"root-on-nfs-debug="\
-    "setenv bootcmd "\
-    "version\\;" \
-    "echo\\;" \
-    "bootp\\;" \
-    "setenv bootargs root=/dev/nfs rw debug " \
-    "nfsroot=\\${serverip}:\\${rootpath} " \
-    "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
-    "run debug-hook\\;" \
-    "run boot-hook\\;" \
-    "bootm\0" \
-"debug-checkout="\
-    "setenv checkhostname;" \
-    "setenv ethaddr 00:09:70:00:00:01;" \
-    "bootp;" \
-    "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
-    "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-    "run debug-hook;" \
-    "run boot-hook;" \
-    "bootm\0" \
-"debug-hook="\
-    "echo ipaddr    ${ipaddr};" \
-    "echo serverip  ${serverip};" \
-    "echo gatewayip ${gatewayip};" \
-    "echo netmask   ${netmask};" \
-    "echo hostname  ${hostname}\0" \
-"ana=run adc ; run dac\0" \
-"adc=run adc-12 ; run adc-34\0" \
-"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
-"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
-"dac=echo ### DAC ; i2c md 11 81 5\0" \
-"boot-hook=echo\0"
-
-/* What should the console's baud rate be? */
-#define CONFIG_BAUDRATE		9600
-
-/* Ethernet MAC address */
-#define CONFIG_ETHADDR		00:09:70:00:00:00
-
-/* The default Ethernet MAC address can be overwritten just once  */
-#ifdef  CONFIG_ETHADDR
-#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
-#endif
-
-/*
- * Define this to do some miscellaneous board-specific initialization.
- */
-#define CONFIG_MISC_INIT_R
-
-/* Set to a positive value to delay for running BOOTCOMMAND */
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
-
-/* Be selective on what keys can delay or stop the autoboot process
- *     To stop	use: " "
- */
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT	"Autobooting...\n"
-#define CONFIG_AUTOBOOT_STOP_STR	" "
-#undef  CONFIG_AUTOBOOT_DELAY_STR
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define DEBUG_BOOTKEYS		0
-
-/* Define a command string that is automatically executed when no character
- * is read on the console interface withing "Boot Delay" after reset.
- */
-#undef	CONFIG_BOOT_ROOT_INITRD		/* Use ram disk for the root file system */
-#define	CONFIG_BOOT_ROOT_NFS		/* Use a NFS mounted root file system */
-
-#ifdef CONFIG_BOOT_ROOT_INITRD
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/ram0 rw quiet " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"run boot-hook;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_INITRD */
-
-#ifdef CONFIG_BOOT_ROOT_NFS
-#define CONFIG_BOOTCOMMAND \
-	"version;" \
-	"echo;" \
-	"bootp;" \
-	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
-	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
-	"run boot-hook;" \
-	"bootm"
-#endif /* CONFIG_BOOT_ROOT_NFS */
-
-#define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
-#define CONFIG_LIB_RAND
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define  CONFIG_BOOTP_DNS
-#define  CONFIG_BOOTP_DNS2
-#define  CONFIG_BOOTP_SEND_HOSTNAME
-
-
-/* undef this to save memory */
-#define CONFIG_SYS_LONGHELP
-
-/* Monitor Command Prompt */
-
-#undef  CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#endif
-
-/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
- * of an image is printed by image commands like bootm or iminfo.
- */
-#define CONFIG_TIMESTAMP
-
-/* If this variable is defined, an environment variable named "ver"
- * is created by U-Boot showing the U-Boot version.
- */
-#define CONFIG_VERSION_VARIABLE
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_SPI
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-
-#undef CONFIG_CMD_KGDB
-
-#ifdef CONFIG_ETHER_ON_FCC
-#define CONFIG_CMD_MII
-#endif
-
-
-/* Where do the internal registers live? */
-#define CONFIG_SYS_IMMR		0xF0000000
-
-#undef	CONFIG_WATCHDOG			/* disable the watchdog */
-
-/*****************************************************************************
- *
- * You should not have to modify any of the following settings
- *
- *****************************************************************************/
-
-#define CONFIG_SACSng		1	/* munged for the SACSng */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_BOOTM_HEADER_QUIET 1        /* Suppress the image header dump    */
-					/* in the bootm command.             */
-#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1       /* Suppress the progress displays,   */
-					/* "## <message>" from the bootm cmd */
-#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1      /* If checkhostname environment is   */
-					/* defined, then the hostname param  */
-					/* validated against checkhostname.  */
-#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up   */
-#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1  /* Use a short random delay value    */
-					/* (limited to maximum of 1024 msec) */
-#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
-					/* Check for abort key presses       */
-					/* at least once in dependent of the */
-					/* CONFIG_BOOTDELAY value.           */
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1        /* Don't print console @ startup     */
-#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1      /* Echo the inverted Ethernet link   */
-					/* state to the fault LED.           */
-#define CONFIG_SYS_FAULT_MII_ADDR 0x02         /* MII addr of the PHY to check for  */
-					/* the Ethernet link state.          */
-#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing  */
-					/* until the TFTP is successful.     */
-#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1  /* After a successful netboot,       */
-					/* turn off the STATUS LEDs.         */
-#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on      */
-					/* incoming data.                    */
-#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100    /* For every XX blocks, output a '#' */
-					/* to signify that tftp is moving.   */
-#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200   /* For every '#' hashes,             */
-					/* flash the status LED.             */
-#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65     /* Only output XX '#'s per line      */
-					/* during the tftp file transfer.    */
-#define CONFIG_SYS_TFTP_PROGESS_QUIET 1        /* Suppress the progress displays    */
-					/* '#'s from the tftp command.       */
-#define CONFIG_SYS_TFTP_STATUS_QUIET 1         /* Suppress the status displays      */
-					/* issued during the tftp command.   */
-#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5        /* How many timeouts TFTP will allow */
-					/* before it gives up.               */
-
-#if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	     */
-#else
-#  define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size	     */
-#endif
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE	  (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
-
-#define CONFIG_SYS_MAXARGS		32	/* max number of command args	*/
-
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	   */
-
-#define CONFIG_SYS_LOAD_ADDR		0x400000   /* default load address */
-
-#define CONFIG_SYS_ALT_MEMTEST                 /* Select full-featured memory test */
-#define CONFIG_SYS_MEMTEST_START	0x2000	/* memtest works from the end of */
-					/* the exception vector table */
-					/* to the end of the DRAM  */
-					/* less monitor and malloc area */
-#define CONFIG_SYS_STACK_USAGE		0x10000 /* Reserve 64k for the stack usage */
-#define CONFIG_SYS_MEM_END_USAGE	( CONFIG_SYS_MONITOR_LEN \
-				+ CONFIG_SYS_MALLOC_LEN \
-				+ CONFIG_ENV_SECT_SIZE \
-				+ CONFIG_SYS_STACK_USAGE )
-
-#define CONFIG_SYS_MEMTEST_END		( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
-				- CONFIG_SYS_MEM_END_USAGE )
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_FLASH0_BASE
-#define CONFIG_SYS_FLASH_SIZE	CONFIG_SYS_FLASH0_SIZE
-#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_SDRAM0_BASE
-#define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_SDRAM0_SIZE
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- */
-#if defined(CONFIG_SYS_SBC_BOOT_LOW)
-#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
-#else
-#  define  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS  (0)
-#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
-
-/* get the HRCW ISB field from CONFIG_SYS_IMMR */
-#define CONFIG_SYS_SBC_HRCW_IMMR	( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
-				  ((CONFIG_SYS_IMMR & 0x01000000) >>  7) | \
-				  ((CONFIG_SYS_IMMR & 0x00100000) >>  4) )
-
-#define CONFIG_SYS_HRCW_MASTER		( HRCW_BPS10				| \
-				  HRCW_DPPC11				| \
-				  CONFIG_SYS_SBC_HRCW_IMMR			| \
-				  HRCW_MMR00				| \
-				  HRCW_LBPC11				| \
-				  HRCW_APPC10				| \
-				  HRCW_CS10PC00				| \
-				  (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111)	| \
-				  CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
-
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1		0
-#define CONFIG_SYS_HRCW_SLAVE2		0
-#define CONFIG_SYS_HRCW_SLAVE3		0
-#define CONFIG_SYS_HRCW_SLAVE4		0
-#define CONFIG_SYS_HRCW_SLAVE5		0
-#define CONFIG_SYS_HRCW_SLAVE6		0
-#define CONFIG_SYS_HRCW_SLAVE7		0
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
- */
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH0_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#  define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
-#undef  CONFIG_SYS_FLASH_PROTECTION		/* use hardware protection		*/
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	(64+4)	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	8000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms)	*/
-
-#ifndef CONFIG_SYS_RAMBOOT
-#  define CONFIG_ENV_IS_IN_FLASH	1
-
-#  ifdef CONFIG_ENV_IN_OWN_SECT
-#    define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#    define CONFIG_ENV_SECT_SIZE	0x10000
-#  else
-#    define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
-#    define CONFIG_ENV_SIZE	0x1000	/* Total Size of Environment Sector	*/
-#    define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sect real size	*/
-#  endif /* CONFIG_ENV_IN_OWN_SECT */
-
-#else
-#  define CONFIG_ENV_IS_IN_NVRAM	1
-#  define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-#  define CONFIG_ENV_SIZE		0x200
-#endif /* CONFIG_SYS_RAMBOOT */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU */
-
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
-#endif
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers			 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control - initially enable both caches and
- * invalidate contents, then the final state leaves only the instruction
- * cache enabled. Note that Power-On and Hard reset invalidate the caches,
- * but Soft reset does not.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT	(HID0_ICE  |\
-			 HID0_DCE  |\
-			 HID0_ICFI |\
-			 HID0_DCI  |\
-			 HID0_IFEM |\
-			 HID0_ABE)
-
-#define CONFIG_SYS_HID0_FINAL	(HID0_ICE  |\
-			 HID0_IFEM |\
-			 HID0_ABE  |\
-			 HID0_EMCP)
-#define CONFIG_SYS_HID2	0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RMR		0
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR		(BCR_ETM)
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-
-#define CONFIG_SYS_SIUMCR	(SIUMCR_DPPC11	|\
-			 SIUMCR_L2CPC00 |\
-			 SIUMCR_APPC10	|\
-			 SIUMCR_MMR00)
-
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined(CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP  |\
-			 SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR	(SYPCR_SWTC |\
-			 SYPCR_BMT  |\
-			 SYPCR_PBME |\
-			 SYPCR_LBME |\
-			 SYPCR_SWRI |\
-			 SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- *-----------------------------------------------------------------------
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- */
-#define CONFIG_SYS_TMCNTSC	(TMCNTSC_SEC |\
-			 TMCNTSC_ALR |\
-			 TMCNTSC_TCF |\
-			 TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR	(PISCR_PS  |\
-			 PISCR_PTF |\
-			 PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SCCR	0
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR	0
-
-/*
- * Initialize Memory Controller:
- *
- * Bank Bus	Machine PortSz	Device
- * ---- ---	------- ------	------
- *  0	60x	GPCM	16 bit	FLASH (primary flash - 2MB)
- *  1	60x	GPCM	-- bit	(Unused)
- *  2	60x	SDRAM	64 bit	SDRAM (DIMM)
- *  3	60x	SDRAM	64 bit	SDRAM (DIMM)
- *  4	60x	GPCM	-- bit	(Unused)
- *  5	60x	GPCM	-- bit	(Unused)
- *  6	60x	GPCM	16 bit	FLASH  (secondary flash - 2MB)
- */
-
-/*-----------------------------------------------------------------------
- * BR0,BR1 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR0,OR1 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 0 - Primary FLASH
- */
-
-/* BR0 is configured as follows:
- *
- *     - Base address of 0x40000000
- *     - 16 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_16			|\
-			 BRx_MS_GPCM_P			|\
-			 BRx_V)
-
-/* OR0 is configured as follows:
- *
- *     - 4 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE)	|\
-			 ORxG_CSNT			|\
-			 ORxG_ACS_DIV1			|\
-			 ORxG_SCY_5_CLK			|\
-			 ORxG_TRLX			|\
-			 ORxG_EHTR)
-
-/*-----------------------------------------------------------------------
- * BR2,BR3 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR2,OR3 - Option Register
- *     Ref: Section 10.3.2 on page 10-16
- *-----------------------------------------------------------------------
- */
-
-/* Bank 2,3 - SDRAM DIMM
- */
-
-/* The BR2 is configured as follows:
- *
- *     - Base address of 0x00000000
- *     - 64 bit port size (60x bus only)
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - SDRAM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
-			 BRx_PS_64			|\
-			 BRx_MS_SDRAM_P			|\
-			 BRx_V)
-
-/* With a 64 MB DIMM, the OR2 is configured as follows:
- *
- *     - 64 MB
- *     - 4 internal banks per device
- *     - Row start address bit is A8 with PSDMR[PBI] = 0
- *     - 12 row address lines
- *     - Back-to-back page mode
- *     - Internal bank interleaving within save device enabled
- */
-#if (CONFIG_SYS_SDRAM0_SIZE == 64)
-#define CONFIG_SYS_OR2_PRELIM	(MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE)	|\
-			 ORxS_BPD_4			|\
-			 ORxS_ROWST_PBI0_A8		|\
-			 ORxS_NUMR_12)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*-----------------------------------------------------------------------
- * PSDMR - 60x Bus SDRAM Mode Register
- *     Ref: Section 10.3.3 on page 10-21
- *-----------------------------------------------------------------------
- */
-
-/* Address that the DIMM SPD memory lives at.
- */
-#define SDRAM_SPD_ADDR 0x50
-
-#if (CONFIG_SYS_SDRAM0_SIZE == 64)
-/* With a 64 MB DIMM, the PSDMR is configured as follows:
- *
- *     - Bank Based Interleaving,
- *     - Refresh Enable,
- *     - Address Multiplexing where A5 is output on A14 pin
- *	 (A6 on A15, and so on),
- *     - use address pins A14-A16 as bank select,
- *     - A9 is output on SDA10 during an ACTIVATE command,
- *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
- *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
- *	 is 3 clocks,
- *     - earliest timing for READ/WRITE command after ACTIVATE command is
- *	 2 clocks,
- *     - earliest timing for PRECHARGE after last data was read is 1 clock,
- *     - earliest timing for PRECHARGE after last data was written is 1 clock,
- *     - CAS Latency is 2.
- */
-#define CONFIG_SYS_PSDMR	(PSDMR_RFEN	      |\
-			 PSDMR_SDAM_A14_IS_A5 |\
-			 PSDMR_BSMA_A14_A16   |\
-			 PSDMR_SDA10_PBI0_A9  |\
-			 PSDMR_RFRC_7_CLK     |\
-			 PSDMR_PRETOACT_3W    |\
-			 PSDMR_ACTTORW_2W     |\
-			 PSDMR_LDOTOPRE_1C    |\
-			 PSDMR_WRC_1C	      |\
-			 PSDMR_CL_2)
-#else
-#error "INVALID SDRAM CONFIGURATION"
-#endif
-
-/*
- * Shoot for approximately 1MHz on the prescaler.
- */
-#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
-#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV64
-#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
-#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
-#else
-#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
-#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV32
-#endif
-#define CONFIG_SYS_PSRT	14
-
-
-/*-----------------------------------------------------------------------
- * BR6 - Base Register
- *     Ref: Section 10.3.1 on page 10-14
- * OR6 - Option Register
- *     Ref: Section 10.3.2 on page 10-18
- *-----------------------------------------------------------------------
- */
-
-/* Bank 6 - Secondary FLASH
- *
- * The secondary FLASH is connected to *CS6
- */
-#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
-
-/* BR6 is configured as follows:
- *
- *     - Base address of 0x60000000
- *     - 16 bit port size
- *     - Data errors checking is disabled
- *     - Read and write access
- *     - GPCM 60x bus
- *     - Access are handled by the memory controller according to MSEL
- *     - Not used for atomic operations
- *     - No data pipelining is done
- *     - Valid
- */
-#  define CONFIG_SYS_BR6_PRELIM  ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
-			   BRx_PS_16			  |\
-			   BRx_MS_GPCM_P		  |\
-			   BRx_V)
-
-/* OR6 is configured as follows:
- *
- *     - 2 MB
- *     - *BCTL0 is asserted upon access to the current memory bank
- *     - *CW / *WE are negated a quarter of a clock earlier
- *     - *CS is output at the same time as the address lines
- *     - Uses a clock cycle length of 5
- *     - *PSDVAL is generated internally by the memory controller
- *	 unless *GTA is asserted earlier externally.
- *     - Relaxed timing is generated by the GPCM for accesses
- *	 initiated to this memory region.
- *     - One idle clock is inserted between a read access from the
- *	 current bank and the next access.
- */
-#  define CONFIG_SYS_OR6_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE)  |\
-			   ORxG_CSNT		       |\
-			   ORxG_ACS_DIV1	       |\
-			   ORxG_SCY_5_CLK	       |\
-			   ORxG_TRLX		       |\
-			   ORxG_EHTR)
-#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
-
-#endif	/* __CONFIG_H */
