From patchwork Fri Jul 4 19:05:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 367206 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 9B8D01400DD for ; Sat, 5 Jul 2014 05:07:18 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3E0ED4B615; Fri, 4 Jul 2014 21:07:11 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1OJC3o4qNrI3; Fri, 4 Jul 2014 21:07:10 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3D1B4A73E0; Fri, 4 Jul 2014 21:06:34 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A32334B5B9 for ; Fri, 4 Jul 2014 21:06:29 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4qS9tV+FIZC7 for ; Fri, 4 Jul 2014 21:06:27 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id 3EBA64A047 for ; Fri, 4 Jul 2014 21:06:20 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s64J68Na017333; Fri, 4 Jul 2014 14:06:08 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s64J687D028657; Fri, 4 Jul 2014 14:06:08 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 4 Jul 2014 14:06:08 -0500 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s64J5tD8032459; Fri, 4 Jul 2014 14:06:06 -0500 From: Pekon Gupta To: Scott Wood , Tom Rini Date: Sat, 5 Jul 2014 00:35:14 +0530 Message-ID: <1404500717-775-5-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.5.1.163.gd7aced9 In-Reply-To: <1404500717-775-1-git-send-email-pekon@ti.com> References: <1404500717-775-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Enric Balletbo Serra , Felten , Lothar@theia.denx.de Subject: [U-Boot] [PATCH v1 4/7] board/ti/am335x: add support for beaglebone NOR Cape X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch updates pin-mux for beaglebone NOR cape [1] This cape has 128Mbits(16MBytes), x16, CFI compatible NOR Flash device. On Beaglebone, GPMC chip-select-0 is shared by both NAND and NOR capes, so only one of them can be enabled at a time from board profile configs. [1] http://elinux.org/Beagleboardtoys:BeagleBone_128Mb_16-Bit_NOR_Module Signed-off-by: Pekon Gupta --- board/ti/am335x/mux.c | 95 +++++++++++++++++++-------------------------------- 1 file changed, 35 insertions(+), 60 deletions(-) diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 439da4b..f6a9b29 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -200,73 +200,46 @@ static struct module_pin_mux nand_pin_mux[] = { {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* BE_CLE */ {-1}, }; -#endif -#if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) +#elif defined(CONFIG_NOR) static struct module_pin_mux bone_norcape_pin_mux[] = { - {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ - {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ - {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */ - {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */ - {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */ - {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */ - {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */ - {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */ - {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */ - {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */ - {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */ - {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */ - {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */ - {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */ - {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */ - {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */ - {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */ - {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */ - {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */ - {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */ - {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */ - {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */ - {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */ - {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */ - {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */ - {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */ - {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */ - {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */ - {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */ - {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */ - {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */ - {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */ - {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */ - {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */ - {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */ - {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */ - - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */ + {OFFSET(gpmc_ad0), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD0 */ + {OFFSET(gpmc_ad1), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD1 */ + {OFFSET(gpmc_ad2), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD2 */ + {OFFSET(gpmc_ad3), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD3 */ + {OFFSET(gpmc_ad4), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD4 */ + {OFFSET(gpmc_ad5), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD5 */ + {OFFSET(gpmc_ad6), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD6 */ + {OFFSET(gpmc_ad7), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD7 */ + {OFFSET(gpmc_ad8), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD8 */ + {OFFSET(gpmc_ad9), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD9 */ + {OFFSET(gpmc_ad10), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD10 */ + {OFFSET(gpmc_ad11), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD11 */ + {OFFSET(gpmc_ad12), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD12 */ + {OFFSET(gpmc_ad13), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD13 */ + {OFFSET(gpmc_ad14), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD14 */ + {OFFSET(gpmc_ad15), MODE(0) | PULLUDDIS | RXACTIVE}, /* AD15 */ + {OFFSET(gpmc_a0), MODE(0) | PULLUDDIS}, /* A0 */ + {OFFSET(gpmc_a1), MODE(0) | PULLUDDIS}, /* A1 */ + {OFFSET(gpmc_a2), MODE(0) | PULLUDDIS}, /* A2 */ + {OFFSET(gpmc_a3), MODE(0) | PULLUDDIS}, /* A3 */ + {OFFSET(gpmc_a4), MODE(0) | PULLUDDIS}, /* A4 */ + {OFFSET(gpmc_a5), MODE(0) | PULLUDDIS}, /* A5 */ + {OFFSET(gpmc_a6), MODE(0) | PULLUDDIS}, /* A6 */ + {OFFSET(gpmc_a7), MODE(0) | PULLUDDIS}, /* A7 */ + {OFFSET(gpmc_csn0), MODE(0) | PULLUDEN | PULLUP_EN}, /* CE */ + {OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* ALE */ + {OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN | PULLDOWN_EN},/* OEn_REN */ + {OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN | PULLDOWN_EN},/* unused */ + {OFFSET(gpmc_wen), MODE(0) | PULLUDEN | PULLDOWN_EN}, /* WEN */ + {OFFSET(gpmc_wait0), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},/*WAIT*/ {-1}, }; #endif #if defined(CONFIG_NOR_BOOT) -static struct module_pin_mux norboot_pin_mux[] = { - {OFFSET(lcd_data1), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data2), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data3), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data4), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data5), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data6), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data7), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data8), MODE(1) | PULLUDDIS}, - {OFFSET(lcd_data9), MODE(1) | PULLUDDIS}, - {-1}, -}; - void enable_norboot_pin_mux(void) { - configure_module_pin_mux(norboot_pin_mux); + configure_module_pin_mux(bone_norcape_pin_mux); } #endif @@ -349,7 +322,7 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); -#elif defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) +#elif defined(CONFIG_NOR) configure_module_pin_mux(bone_norcape_pin_mux); #else configure_module_pin_mux(mmc1_pin_mux); @@ -393,6 +366,8 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); +#elif defined(CONFIG_NOR) + configure_module_pin_mux(bone_norcape_pin_mux); #else configure_module_pin_mux(mmc1_pin_mux); #endif