@@ -93,6 +93,10 @@ struct davinci_emif_regs {
#define DAVINCI_ABCR_ASIZE_16BIT 1
#define DAVINCI_ABCR_ASIZE_8BIT 0
+/* Layouts */
+#define NAND_DAVINCI_4BIT_LAYOUT 0
+#define NAND_KEYSTONE_RBL_4BIT_LAYOUT 1
+
void davinci_nand_init(struct nand_chip *nand);
#endif
@@ -305,6 +305,100 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
#endif
};
+#if defined(CONFIG_CMD_NAND_ECCLAYOUT)
+#if defined(CONFIG_SYS_NAND_PAGE_2K)
+static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
+ .eccbytes = 40,
+ .eccpos = {
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4, },
+ {.offset = 16, .length = 6, },
+ {.offset = 32, .length = 6, },
+ {.offset = 48, .length = 6, },
+ },
+};
+#elif defined(CONFIG_SYS_NAND_PAGE_4K)
+static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
+ .eccbytes = 80,
+ .eccpos = {
+ 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
+ 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
+ 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
+ 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
+ 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
+ },
+ .oobfree = {
+ {.offset = 2, .length = 4, },
+ {.offset = 16, .length = 6, },
+ {.offset = 32, .length = 6, },
+ {.offset = 48, .length = 6, },
+ {.offset = 64, .length = 6, },
+ {.offset = 80, .length = 6, },
+ {.offset = 96, .length = 6, },
+ {.offset = 112, .length = 6, },
+ },
+};
+#endif
+
+struct nand_ecclayout *davinci_nand_ecclayouts[] = {
+ &nand_davinci_4bit_layout_oobfirst,
+ &nand_keystone_rbl_4bit_layout_oobfirst,
+};
+
+int board_nand_get_ecclayout_idx(struct nand_chip *nand,
+ struct nand_ecclayout *layout)
+{
+ int i;
+
+ if (!layout)
+ return -1;
+
+ for (i = 0; i < ARRAY_SIZE(davinci_nand_ecclayouts); i++)
+ if (davinci_nand_ecclayouts[i] == layout)
+ return i;
+
+ return -1;
+}
+
+struct nand_ecclayout *board_nand_get_ecclayout(int idx)
+{
+ if ((idx >= 0) && (idx < ARRAY_SIZE(davinci_nand_ecclayouts)))
+ return davinci_nand_ecclayouts[idx];
+ else
+ return NULL;
+}
+
+int board_nand_set_ecclayout(struct mtd_info *mtd, int idx)
+{
+ int i;
+ struct nand_ecclayout *layout;
+ struct nand_chip *nand = mtd->priv;
+
+ if (idx < 0 || idx >= ARRAY_SIZE(davinci_nand_ecclayouts))
+ return -1;
+
+ layout = davinci_nand_ecclayouts[idx];
+
+ layout->oobavail = 0;
+ for (i = 0; layout->oobfree[i].length &&
+ i < ARRAY_SIZE(layout->oobfree); i++)
+ layout->oobavail += layout->oobfree[i].length;
+
+ mtd->oobavail = layout->oobavail;
+ nand->ecc.layout = layout;
+
+ return 0;
+}
+#endif /* CONFIG_CMD_NAND_ECCLAYOUT */
+
static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
u32 val;