From patchwork Wed Jun 4 08:19:26 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hannes Schmelzer X-Patchwork-Id: 355776 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B953214007C for ; Wed, 4 Jun 2014 18:48:07 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7477D4B831; Wed, 4 Jun 2014 10:48:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Oe8cWPsR-Rdo; Wed, 4 Jun 2014 10:48:03 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B076F4B84A; Wed, 4 Jun 2014 10:47:55 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1A7244B6DB for ; Wed, 4 Jun 2014 10:47:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Le9hJvRwISlR for ; Wed, 4 Jun 2014 10:47:46 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from s15287728.onlinehome-server.info (hamspirit.at [87.106.47.214]) by theia.denx.de (Postfix) with ESMTP id A58DF4B91E for ; Wed, 4 Jun 2014 10:47:42 +0200 (CEST) Received: from localhost (s15287728.onlinehome-server.info [127.0.0.1]) by s15287728.onlinehome-server.info (Postfix) with ESMTP id 238838F480B1; Wed, 4 Jun 2014 08:19:47 +0000 (UTC) Received: from s15287728.onlinehome-server.info ([127.0.0.1]) by localhost (s15287728.onlinehome-server.info [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fwpSdynZbidQ; Wed, 4 Jun 2014 08:19:41 +0000 (UTC) Received: from hannes-werkstatt.scm.lan (194-96-34-183.adsl.highway.telekom.at [194.96.34.183]) by s15287728.onlinehome-server.info (Postfix) with ESMTP id 8C65C8F480B0; Wed, 4 Jun 2014 08:19:41 +0000 (UTC) From: Hannes Petermaier To: u-boot@lists.denx.de Date: Wed, 4 Jun 2014 10:19:26 +0200 Message-Id: <1401869966-7224-1-git-send-email-oe5hpm@oevsv.at> X-Mailer: git-send-email 1.7.9.5 Cc: trini@ti.com, Hannes Petermaier Subject: [U-Boot] [PATCH] arch-am33xx: Add defines for timer0-7 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de For usage of timer6 within B&R we need this defines to enable clock modules and clk-source. Also the 'Timer register bits' are expanded. By the way we add defines for all timers within AM335x SoC. Cc: trini@ti.com Signed-off-by: Hannes Petermaier --- arch/arm/include/asm/arch-am33xx/cpu.h | 35 ++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index d9f0306..aa10fab 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -26,7 +26,17 @@ #define TCLR_PRE BIT(5) /* Pre-scaler enable */ #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ - +#define TCLR_CE BIT(6) /* compare mode enable */ +#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */ +#define TCLR_TCM BIT(8) /* edge detection of input pin*/ +#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */ +#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/ +#define TCLR_CAPTMODE BIT(13) /* capture mode */ +#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */ + +#define TCFG_RESET BIT(0) /* software reset */ +#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ +#define TCFG_IDLEMOD_SHIFT (2) /* power management */ /* device type */ #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) #define TST_DEVICE 0x0 @@ -87,7 +97,8 @@ struct cm_wkuppll { unsigned int wkctrlclkctrl; /* offset 0x04 */ unsigned int wkgpio0clkctrl; /* offset 0x08 */ unsigned int wkl4wkclkctrl; /* offset 0x0c */ - unsigned int resv2[4]; + unsigned int timer0clkctrl; /* offset 0x10 */ + unsigned int resv2[3]; unsigned int idlestdpllmpu; /* offset 0x20 */ unsigned int resv3[2]; unsigned int clkseldpllmpu; /* offset 0x2c */ @@ -121,7 +132,9 @@ struct cm_wkuppll { unsigned int wkup_uart0ctrl; /* offset 0xB4 */ unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ unsigned int wkup_adctscctrl; /* offset 0xBC */ - unsigned int resv12[6]; + unsigned int resv12; + unsigned int timer1clkctrl; /* offset 0xC4 */ + unsigned int resv13[4]; unsigned int divm6dpllcore; /* offset 0xD8 */ }; @@ -178,7 +191,9 @@ struct cm_perpll { unsigned int epwmss2clkctrl; /* offset 0xD8 */ unsigned int l3instrclkctrl; /* offset 0xDC */ unsigned int l3clkctrl; /* Offset 0xE0 */ - unsigned int resv8[4]; + unsigned int resv8[2]; + unsigned int timer5clkctrl; /* offset 0xEC */ + unsigned int timer6clkctrl; /* offset 0xF0 */ unsigned int mmc1clkctrl; /* offset 0xF4 */ unsigned int mmc2clkctrl; /* offset 0xF8 */ unsigned int resv9[8]; @@ -191,9 +206,17 @@ struct cm_perpll { /* Encapsulating Display pll registers */ struct cm_dpll { - unsigned int resv1[2]; + unsigned int resv1; + unsigned int clktimer7clk; /* offset 0x04 */ unsigned int clktimer2clk; /* offset 0x08 */ - unsigned int resv2[10]; + unsigned int clktimer3clk; /* offset 0x0C */ + unsigned int clktimer4clk; /* offset 0x10 */ + unsigned int resv2; + unsigned int clktimer5clk; /* offset 0x18 */ + unsigned int clktimer6clk; /* offset 0x1C */ + unsigned int resv3[2]; + unsigned int clktimer1clk; /* offset 0x28 */ + unsigned int resv4[2]; unsigned int clklcdcpixelclk; /* offset 0x34 */ }; #else