diff mbox

[U-Boot,v2,12/12] sunxi: Add support for using MII phy-s with the GMAC nic

Message ID 1401824522-11353-13-git-send-email-hdegoede@redhat.com
State Superseded
Delegated to: Albert ARIBAUD
Headers show

Commit Message

Hans de Goede June 3, 2014, 7:42 p.m. UTC 
From: Chen-Yu Tsai <wens@csie.org>

Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII
phy together with the GMAC nic found in the A20 SoC, add support for this
(this will get used when we add these boards in a later patch).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 board/sunxi/gmac.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Ian Campbell June 5, 2014, 6:50 p.m. UTC | #1 
On Tue, 2014-06-03 at 21:42 +0200, Hans de Goede wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII
> phy together with the GMAC nic found in the A20 SoC, add support for this
> (this will get used when we add these boards in a later patch).
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>
diff mbox

Patch

diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c
index e48328d..e7ff952 100644
--- a/board/sunxi/gmac.c
+++ b/board/sunxi/gmac.c
@@ -16,17 +16,28 @@  int sunxi_gmac_initialize(bd_t *bis)
 	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
 
 	/* Set MII clock */
+#ifdef CONFIG_RGMII
 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
 		CCM_GMAC_CTRL_GPIT_RGMII);
+#else
+	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
+		CCM_GMAC_CTRL_GPIT_MII);
+#endif
 
 	/* Configure pin mux settings for GMAC */
 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
+#ifdef CONFIG_RGMII
 		/* skip unused pins in RGMII mode */
 		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
 			continue;
+#endif
 		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
 		sunxi_gpio_set_drv(pin, 3);
 	}
 
+#ifdef CONFIG_RGMII
 	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
+#else
+	return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
+#endif
 }