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Mon, 26 May 2014 22:51:13 +0900 (KST) X-AuditID: cbfee690-b7fb56d000003439-c8-538346d15134 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 4F.69.08203.1D643835; Mon, 26 May 2014 22:51:13 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N66001OMP42EC00@mmp1.samsung.com>; Mon, 26 May 2014 22:51:13 +0900 (KST) From: Akshay Saraswat To: u-boot@lists.denx.de Date: Mon, 26 May 2014 19:19:05 +0530 Message-id: <1401112145-9265-1-git-send-email-akshay.s@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWyRsSkTveiW3Owwa93Ghan/jxmtDi77CCb xdQH5xgtvm3Zxmix/PVGdou3ezvZLf4tm8XuwO4xu+Eii8fOWXfZPRZsKvU4e2cHo0ffllWM AaxRXDYpqTmZZalF+nYJXBlzW8oK/ilUdPd9ZGlgbJPuYuTkkBAwkbiz4gYbhC0mceHeeiCb i0NIYCmjxO/t6xhhirbO+wWVWMQo8e3edxYIZwKTxNHvK5hAqtgEdCS2L/nODmKLCEhI/Oq/ yghSxCywmlFi4o/bzCAJYQEfiRUzz4PtYxFQlZizbD1YnFfAWWLvsQ1AgziA1ilIzJlkA9Ir IdDMLrH191t2iHoBiW+TD7FA1MhKbDrADHGdpMTBFTdYJjAKLmBkWMUomlqQXFCclF5kolec mFtcmpeul5yfu4kRGLan/z2bsIPx3gHrQ4zJQOMmMkuJJucDwz6vJN7Q2MzIwtTE1NjI3NKM NGElcV61R0lBQgLpiSWp2ampBalF8UWlOanFhxiZODilGhizA37eNL7SnT/z2aXDPV90b/L/ KnMoj48Q2KYluLNlzpSY2yzzNJSdxWYsEV4z/T9vmpvWdoHwT77/NipJ7Cg02rihzJhzUtT+ Ds/5HtkHlpk6rv2u3jT73qm9h40sgxISLT9MDaz6yp1Y9aln5VNvx/+NVX8u1mxlUFNjP/3q 9eQ715dmOoopsRRnJBpqMRcVJwIAxSZrcXECAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNIsWRmVeSWpSXmKPExsVy+t9jAd2Lbs3BBvduyFqc+vOY0eLssoNs FlMfnGO0+LZlG6PF8tcb2S3e7u1kt/i3bBa7A7vH7IaLLB47Z91l91iwqdTj7J0djB59W1Yx BrBGNTDaZKQmpqQWKaTmJeenZOal2yp5B8c7x5uaGRjqGlpamCsp5CXmptoqufgE6Lpl5gDd oaRQlphTChQKSCwuVtK3wzQhNMRN1wKmMULXNyQIrsfIAA0krGHMmNtSVvBPoaK77yNLA2Ob dBcjJ4eEgInE1nm/2CBsMYkL99YD2VwcQgKLGCW+3fvOAuFMYJI4+n0FE0gVm4COxPYl39lB bBEBCYlf/VcZQYqYBVYzSkz8cZsZJCEs4COxYuZ5sLEsAqoSc5atB4vzCjhL7D22AWgQB9A6 BYk5k2wmMHIvYGRYxSiaWpBcUJyUnmuoV5yYW1yal66XnJ+7iREcFc+kdjCubLA4xCjAwajE w3vAuylYiDWxrLgy9xCjBAezkgivFmdzsBBvSmJlVWpRfnxRaU5q8SHGZKDlE5mlRJPzgRGb VxJvaGxibmpsamliYWJmSZqwkjjvgVbrQCGB9MSS1OzU1ILUIpgtTBycUg2Mcw6ccZ1wYN33 cz+OGjdYXY/zbiz9bLp18mnLR8d009VsVvzitC/bd4H9suF0rXcGrS9+BnAteHbLgu2Pv3Ko tZ5l3gQBo/N9DcW7JObO+/Dr/qW1JtmCf6IPGIVpSnyef25Gp529PM+rpv8T+4r2shglbjm4 56bM7/PMt+3Cpm8ImFly5CtnuxJLcUaioRZzUXEiAMXE9EnOAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: u-boot-review@google.com, vbendeb@chromium.org Subject: [U-Boot] [PATCH v2 3/4] DMC: exynos5420: Gate CLKM to when reading PHY_CON13 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Doug Anderson From experiments it appears that PHY_CON13 is glitchy if we sample it when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: Doug Anderson Signed-off-by: Akshay Saraswat Acked-by: Simon Glass Tested-by: Simon Glass --- Changes since v1: - Added "Acked-by". arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 43 +++++++++++++++++++++++++++---- arch/arm/cpu/armv7/exynos/exynos5_setup.h | 1 + 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index 1d6048c..13003b8 100644 --- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -230,6 +230,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) struct exynos5420_dmc *drex0, *drex1; struct exynos5420_tzasc *tzasc0, *tzasc1; uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; + uint32_t lock0_info, lock1_info; int chip; int i; @@ -391,7 +392,41 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) */ dmc_config_mrs(mem, &drex0->directcmd); dmc_config_mrs(mem, &drex1->directcmd); - } else { + } + + /* + * Get PHY_CON13 from both phys. Gate CLKM around reading since + * PHY_CON13 is glitchy when CLKM is running. We're paranoid and + * wait until we get a "fine lock", though a coarse lock is probably + * OK (we only use the coarse numbers below). We try to gate the + * clock for as short a time as possible in case SDRAM is somehow + * sensitive. sdelay(10) in the loop is arbitrary to make sure + * there is some time for PHY_CON13 to get updated. In practice + * no delay appears to be needed. + */ + val = readl(&clk->gate_bus_cdrex); + while (true) { + writel(val & ~0x1, &clk->gate_bus_cdrex); + lock0_info = readl(&phy0_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + while (true) { + writel(val & ~0x2, &clk->gate_bus_cdrex); + lock1_info = readl(&phy1_ctrl->phy_con13); + writel(val, &clk->gate_bus_cdrex); + + if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED) + break; + + sdelay(10); + } + + if (!reset) { /* * During Suspend-Resume & S/W-Reset, as soon as PMU releases * pad retention, CKE goes high. This causes memory contents @@ -442,15 +477,13 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET); writel(val, &phy1_ctrl->phy_con1); - n_lock_r = readl(&phy0_ctrl->phy_con13); - n_lock_w_phy0 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy0_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy0; writel(n_lock_r, &phy0_ctrl->phy_con12); - n_lock_r = readl(&phy1_ctrl->phy_con13); - n_lock_w_phy1 = (n_lock_r & CTRL_LOCK_COARSE_MASK) >> 2; + n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2; n_lock_r = readl(&phy1_ctrl->phy_con12); n_lock_r &= ~CTRL_DLL_ON; n_lock_r |= n_lock_w_phy1; diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h index 4542bd1..583be27 100644 --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -284,6 +284,7 @@ #define CTRL_DLL_ON (1 << 5) #define CTRL_FORCE_MASK (0x7F << 8) #define CTRL_LOCK_COARSE_MASK (0x7F << 10) +#define CTRL_FINE_LOCKED 0x7 #define CTRL_OFFSETD_RESET_VAL 0x8 #define CTRL_OFFSETD_VAL 0x7F