From patchwork Thu May 22 21:54:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 351627 X-Patchwork-Delegate: yorksun@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6482E140080 for ; Fri, 23 May 2014 07:55:19 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8C4E34B6DB; Thu, 22 May 2014 23:55:16 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6BvVGfIaKIhS; Thu, 22 May 2014 23:55:16 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E93D4B6CA; Thu, 22 May 2014 23:55:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EB70B4B6CA for ; Thu, 22 May 2014 23:55:07 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DV6NvwW617X0 for ; Thu, 22 May 2014 23:55:04 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1blp0186.outbound.protection.outlook.com [207.46.163.186]) by theia.denx.de (Postfix) with ESMTPS id 3E7EC4B6C7 for ; Thu, 22 May 2014 23:54:59 +0200 (CEST) Received: from CH1PR03CA003.namprd03.prod.outlook.com (10.255.156.148) by BY2PR03MB159.namprd03.prod.outlook.com (10.242.36.18) with Microsoft SMTP Server (TLS) id 15.0.944.11; Thu, 22 May 2014 21:54:45 +0000 Received: from BN1AFFO11FD038.protection.gbl (10.255.156.132) by CH1PR03CA003.outlook.office365.com (10.255.156.148) with Microsoft SMTP Server (TLS) id 15.0.944.11 via Frontend Transport; Thu, 22 May 2014 21:54:44 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.1) by BN1AFFO11FD038.mail.protection.outlook.com (10.58.52.242) with Microsoft SMTP Server (TLS) id 15.0.949.9 via Frontend Transport; Thu, 22 May 2014 21:54:44 +0000 Received: from oslab-l1.am.freescale.net ([10.214.84.236]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s4MLsgO1005817; Thu, 22 May 2014 14:54:43 -0700 From: York Sun To: Date: Thu, 22 May 2014 14:54:40 -0700 Message-ID: <1400795680-482-1-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.1; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(77156001)(50986999)(4396001)(50226001)(81342001)(102836001)(77982001)(62966002)(87286001)(26826002)(76482001)(89996001)(74662001)(33646001)(36756003)(77096999)(6806004)(21056001)(46102001)(80022001)(81542001)(79102001)(86362001)(93916002)(92566001)(23676002)(50466002)(92726001)(99396002)(74502001)(19580395003)(31966008)(20776003)(87936001)(88136002)(19580405001)(85852003)(47776003)(83072002)(83322001)(64706001)(44976005); DIR:OUT; SFP:; SCL:1; SRVR:BY2PR03MB159; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:gate-tx3.freescale.com; MX:1; A:1; LANG:en; X-Forefront-PRVS: 021975AE46 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.168.1 as permitted sender) receiver=; client-ip=192.88.168.1; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.1) smtp.mailfrom=yorksun@freescale.com; X-OriginatorOrg: freescale.com Cc: York Sun Subject: [U-Boot] [PATCH] powerpc/mpc85xx: Add workaround for DDR erratum A004508 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de When the DDR controller is initialized below a junction temperature of 0°C and then operated above a junction temperature of 65°C, the DDR controller may cause receive data errors, resulting ECC errors and/or corrupted data. This erratum applies to the following SoCs and their variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023, P2020. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 18 ++++++++++++++++++ drivers/ddr/fsl/ctrl_regs.c | 9 +++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 3d37a76..f69c834 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -231,6 +231,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) puts("Work-around for Erratum NMG ETSEC129 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + puts("Work-around for Erratum A004508 enabled\n"); +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 puts("Work-around for Erratum A004510 enabled\n"); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 34fc8fb..c9fd2a5 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -38,6 +38,7 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8540) @@ -122,6 +123,7 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_MPC8572) @@ -132,6 +134,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1010) @@ -154,6 +157,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A007075 #define CONFIG_SYS_FSL_ERRATUM_A006261 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 @@ -171,6 +175,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1012 is single core version of P1021 */ @@ -188,6 +193,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1013 is single core version of P1022 */ @@ -202,6 +208,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1014) @@ -219,6 +226,7 @@ #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_A004508 /* P1017 is single core version of P1023 */ #elif defined(CONFIG_P1017) @@ -234,6 +242,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1020) @@ -246,6 +255,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -264,6 +274,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -278,6 +289,7 @@ #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_FSL_SATA_ERRATUM_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P1023) @@ -293,6 +305,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 @@ -309,6 +322,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P1025 is lower end variant of P1021 */ @@ -326,6 +340,7 @@ #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 /* P2010 is single core version of P2020 */ @@ -338,6 +353,7 @@ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #elif defined(CONFIG_P2020) @@ -353,8 +369,10 @@ #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_RMU #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CONFIG_SYS_FSL_ERRATUM_A004508 #define CONFIG_SYS_FSL_ERRATUM_A005125 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 78e82bb..38654ff 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2304,5 +2304,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, ddr->debug[2] = 0x00000400; ddr->debug[4] = 0xff800000; #endif + + if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) { +#ifdef CONFIG_SYS_FSL_ERRATUM_A004508 + ddr->debug[2] |= 0x00000200; /* set bit 22 */ +#else + puts("Warning: Workaround for A004508 is not enabled.\n"); +#endif + } + return check_fsl_memctl_config_regs(ddr); }