diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5554615..933a464 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -6,7 +6,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5250-snow.dtb \
 	exynos5250-smdk5250.dtb \
-	exynos5420-smdk5420.dtb
+	exynos5420-smdk5420.dtb \
+	exynos5420-peach-pit.dtb
 dtb-$(CONFIG_MX6) += imx6q-sabreauto.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
new file mode 100644
index 0000000..8d148af
--- /dev/null
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -0,0 +1,127 @@
+/*
+ * SAMSUNG/GOOGLE Peach-Pit board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "exynos54xx.dtsi"
+
+/ {
+	model = "Samsung/Google Peach Pit board based on Exynos5420";
+
+	compatible = "google,pit-rev#", "google,pit",
+		"google,peach", "samsung,exynos5420", "samsung,exynos5";
+
+	config {
+		google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
+		hwid = "PIT TEST A-A 7848";
+		lazy-init = <1>;
+	};
+
+	aliases {
+		serial0 = "/serial@12C30000";
+		console = "/serial@12C30000";
+		pmic = "/i2c@12ca0000";
+	};
+
+	dmc {
+		mem-manuf = "samsung";
+		mem-type = "ddr3";
+		clock-frequency = <800000000>;
+		arm-frequency = <1700000000>;
+	};
+
+	tmu@10060000 {
+		samsung,min-temp	= <25>;
+		samsung,max-temp	= <125>;
+		samsung,start-warning	= <95>;
+		samsung,start-tripping	= <105>;
+		samsung,hw-tripping	= <110>;
+		samsung,efuse-min-value	= <40>;
+		samsung,efuse-value	= <55>;
+		samsung,efuse-max-value	= <100>;
+		samsung,slope		= <274761730>;
+		samsung,dc-value	= <25>;
+	};
+
+	/* MAX77802 is on i2c bus 4 */
+	i2c@12ca0000 {
+		clock-frequency = <400000>;
+		power-regulator@9 {
+			compatible = "maxim,max77802-pmic";
+			reg = <0x9>;
+		};
+	};
+
+	i2c@12cd0000 { /* i2c7 */
+		clock-frequency = <100000>;
+	       soundcodec@20 {
+	              reg = <0x20>;
+	              compatible = "maxim,max98090-codec";
+	       };
+	};
+
+        sound@3830000 {
+                samsung,codec-type = "max98090";
+        };
+
+	i2c@12e10000 { /* i2c9 */
+		clock-frequency = <400000>;
+                tpm@20 {
+                        compatible = "infineon,slb9645-tpm";
+                        reg = <0x20>;
+		};
+	};
+
+	spi@12d30000 { /* spi1 */
+		spi-max-frequency = <50000000>;
+		firmware_storage_spi: flash@0 {
+			reg = <0>;
+
+			/*
+			 * A region for the kernel to store a panic event
+			 * which the firmware will add to the log.
+			*/
+			elog-panic-event-offset = <0x01e00000 0x100000>;
+
+			elog-shrink-size = <0x400>;
+			elog-full-threshold = <0xc00>;
+		};
+	};
+
+	spi@12d40000 { /* spi2 */
+		spi-max-frequency = <4000000>;
+		spi-deactivate-delay = <200>;
+		cros-ec@0 {
+			reg = <0>;
+			compatible = "google,cros-ec";
+			spi-half-duplex;
+			spi-max-timeout-ms = <1100>;
+			spi-frame-header = <0xec>;
+			ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
+
+			/*
+			 * This describes the flash memory within the EC. Note
+			 * that the STM32L flash erases to 0, not 0xff.
+			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			flash@8000000 {
+				reg = <0x08000000 0x20000>;
+				erase-value = <0>;
+			};
+		};
+	};
+
+	xhci@12000000 {
+		samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
+	};
+
+	xhci@12400000 {
+		samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
+	};
+};
diff --git a/arch/arm/dts/exynos5420-smdk5420.dts b/arch/arm/dts/exynos5420-smdk5420.dts
index d739763..1bc6256 100644
--- a/arch/arm/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/dts/exynos5420-smdk5420.dts
@@ -8,7 +8,7 @@
  */
 
 /dts-v1/;
-/include/ "exynos5420.dtsi"
+/include/ "exynos54xx.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5420 board based on EXYNOS5420";
@@ -19,27 +19,6 @@
 	};
 
 	aliases {
-		i2c0 = "/i2c@12c60000";
-		i2c1 = "/i2c@12c70000";
-		i2c2 = "/i2c@12c80000";
-		i2c3 = "/i2c@12c90000";
-		i2c4 = "/i2c@12ca0000";
-		i2c5 = "/i2c@12cb0000";
-		i2c6 = "/i2c@12cc0000";
-		i2c7 = "/i2c@12cd0000";
-		i2c8 = "/i2c@12e00000";
-		i2c9 = "/i2c@12e10000";
-		i2c10 = "/i2c@12e20000";
-		spi0 = "/spi@12d20000";
-		spi1 = "/spi@12d30000";
-		spi2 = "/spi@12d40000";
-		spi3 = "/spi@131a0000";
-		spi4 = "/spi@131b0000";
-		mmc0 = "/mmc@12200000";
-		mmc1 = "/mmc@12210000";
-		mmc2 = "/mmc@12220000";
-		xhci0 = "/xhci@12000000";
-		xhci1 = "/xhci@12400000";
 		serial0 = "/serial@12C30000";
 		console = "/serial@12C30000";
 	};
diff --git a/arch/arm/dts/exynos5420.dtsi b/arch/arm/dts/exynos5420.dtsi
deleted file mode 100644
index 02ead61..0000000
--- a/arch/arm/dts/exynos5420.dtsi
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2013 SAMSUNG Electronics
- * SAMSUNG EXYNOS5420 SoC device tree source
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/include/ "exynos5.dtsi"
-
-/ {
-	config {
-		machine-arch-id = <4151>;
-	};
-
-	i2c@12ca0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CA0000 0x100>;
-		interrupts = <0 60 0>;
-	};
-
-	i2c@12cb0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CB0000 0x100>;
-		interrupts = <0 61 0>;
-	};
-
-	i2c@12cc0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CC0000 0x100>;
-		interrupts = <0 62 0>;
-	};
-
-	i2c@12cd0000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12CD0000 0x100>;
-		interrupts = <0 63 0>;
-	};
-
-	i2c@12e00000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12E00000 0x100>;
-		interrupts = <0 87 0>;
-	};
-
-	i2c@12e10000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12E10000 0x100>;
-		interrupts = <0 88 0>;
-	};
-
-	i2c@12e20000 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "samsung,exynos5-hsi2c";
-		reg = <0x12E20000 0x100>;
-		interrupts = <0 203 0>;
-	};
-};
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
new file mode 100644
index 0000000..b9f8e0b
--- /dev/null
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2013 SAMSUNG Electronics
+ * SAMSUNG EXYNOS5420 SoC device tree source
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "exynos5.dtsi"
+
+/ {
+	config {
+		machine-arch-id = <4151>;
+	};
+
+	aliases {
+		i2c0 = "/i2c@12c60000";
+		i2c1 = "/i2c@12c70000";
+		i2c2 = "/i2c@12c80000";
+		i2c3 = "/i2c@12c90000";
+		i2c4 = "/i2c@12ca0000";
+		i2c5 = "/i2c@12cb0000";
+		i2c6 = "/i2c@12cc0000";
+		i2c7 = "/i2c@12cd0000";
+		i2c8 = "/i2c@12e00000";
+		i2c9 = "/i2c@12e10000";
+		i2c10 = "/i2c@12e20000";
+		spi0 = "/spi@12d20000";
+		spi1 = "/spi@12d30000";
+		spi2 = "/spi@12d40000";
+		spi3 = "/spi@131a0000";
+		spi4 = "/spi@131b0000";
+		mmc0 = "/mmc@12200000";
+		mmc1 = "/mmc@12210000";
+		mmc2 = "/mmc@12220000";
+		xhci0 = "/xhci@12000000";
+		xhci1 = "/xhci@12400000";
+	};
+
+	i2c@12ca0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CA0000 0x100>;
+		interrupts = <0 60 0>;
+	};
+
+	i2c@12cb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CB0000 0x100>;
+		interrupts = <0 61 0>;
+	};
+
+	i2c@12cc0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CC0000 0x100>;
+		interrupts = <0 62 0>;
+	};
+
+	i2c@12cd0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12CD0000 0x100>;
+		interrupts = <0 63 0>;
+	};
+
+	i2c@12e00000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E00000 0x100>;
+		interrupts = <0 87 0>;
+	};
+
+	i2c@12e10000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E10000 0x100>;
+		interrupts = <0 88 0>;
+	};
+
+	i2c@12e20000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "samsung,exynos5-hsi2c";
+		reg = <0x12E20000 0x100>;
+		interrupts = <0 203 0>;
+	};
+
+	mmc@12200000 {
+		samsung,bus-width = <8>;
+		samsung,timing = <1 3 3>;
+		samsung,removable = <0>;
+		samsung,pre-init;
+	};
+
+	mmc@12210000 {
+		status = "disabled";
+	};
+
+	mmc@12220000 {
+		samsung,bus-width = <4>;
+		samsung,timing = <1 2 3>;
+		samsung,removable = <1>;
+	};
+
+	mmc@12230000 {
+		status = "disabled";
+	};
+
+	fimd@14400000 {
+		/* sysmmu is not used in U-Boot */
+		samsung,disable-sysmmu;
+	};
+
+	dp@145b0000 {
+		samsung,lt-status = <0>;
+
+		samsung,master-mode = <0>;
+		samsung,bist-mode = <0>;
+		samsung,bist-pattern = <0>;
+		samsung,h-sync-polarity = <0>;
+		samsung,v-sync-polarity = <0>;
+		samsung,interlaced = <0>;
+		samsung,color-space = <0>;
+		samsung,dynamic-range = <0>;
+		samsung,ycbcr-coeff = <0>;
+		samsung,color-depth = <1>;
+	};
+
+	dmc {
+		mem-type = "ddr3";
+	};
+
+	xhci1: xhci@12400000 {
+		compatible = "samsung,exynos5250-xhci";
+		reg = <0x12400000 0x10000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		phy {
+			compatible = "samsung,exynos5250-usb3-phy";
+			reg = <0x12500000 0x100>;
+		};
+	};
+};
diff --git a/boards.cfg b/boards.cfg
index 880d972..4423231 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -289,6 +289,7 @@ Active  arm         armv7          exynos      samsung         origen
 Active  arm         armv7          exynos      samsung         smdk5250            smdk5250                             -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         smdk5250            snow                                 -                                                                                                                                 Rajeshwari Shinde <rajeshwari.s@samsung.com>
 Active  arm         armv7          exynos      samsung         smdk5420            smdk5420                             -                                                                                                                                 Rajeshwari Shinde <rajeshwari.s@samsung.com>
+Active  arm         armv7          exynos      samsung         smdk5420            peach-pit                             -                                                                                                                                 Akshay Saraswat <akshay.s@samsung.com>
 Active  arm         armv7          exynos      samsung         smdkv310            smdkv310                             -                                                                                                                                 Chander Kashyap <k.chander@samsung.com>
 Active  arm         armv7          exynos      samsung         trats               trats                                -                                                                                                                                 Lukasz Majewski <l.majewski@samsung.com>
 Active  arm         armv7          exynos      samsung         trats2              trats2                               -                                                                                                                                 Piotr Wilczek <p.wilczek@samsung.com>
diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420.h
new file mode 100644
index 0000000..3a28bbc
--- /dev/null
+++ b/include/configs/exynos5420.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG EXYNOS5420 SoC
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS5420_H
+#define __CONFIG_EXYNOS5420_H
+
+#define CONFIG_EXYNOS5420		/* which is in a Exynos5 Family */
+
+#define MACH_TYPE_SMDK5420	8002
+#define CONFIG_MACH_TYPE	MACH_TYPE_SMDK5420
+
+#define CONFIG_VAR_SIZE_SPL
+
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_TEXT_BASE		0x23E00000
+#ifdef CONFIG_VAR_SIZE_SPL
+#define CONFIG_SPL_TEXT_BASE		0x02024410
+#else
+#define CONFIG_SPL_TEXT_BASE		0x02024400
+#endif
+#define CONFIG_IRAM_TOP			0x02074000
+
+#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
+
+#define CONFIG_MAX_I2C_NUM	11
+
+/* Enable FIT support and comparison */
+#define CONFIG_FIT
+#define CONFIG_FIT_BEST_MATCH
+
+#define CONFIG_BOARD_REV_GPIO_COUNT	2
+
+#define CONFIG_BOOTCOMMAND	"mmc read 20007000 451 2000; bootm 20007000"
+
+/*
+ * Put the initial stack pointer 1KB below this to allow room for the
+ * SPL marker. This value is arbitrary, but gd_t is placed starting here.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
+
+#endif	/* __CONFIG_EXYNOS5420_H */
diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h
new file mode 100644
index 0000000..638b68b
--- /dev/null
+++ b/include/configs/peach-pit.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics
+ *
+ * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_PEACH_PIT_H
+#define __CONFIG_PEACH_PIT_H
+
+#include <configs/exynos5-dt.h>
+
+#include <configs/exynos5420.h>
+
+#define CONFIG_CHROMEOS_PEACH
+
+#undef CONFIG_DEFAULT_DEVICE_TREE
+#define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-peach-pit
+
+/* select serial console configuration */
+#define CONFIG_SERIAL3		/* use SERIAL 3 */
+
+#define CONFIG_SYS_PROMPT	"Peach # "
+#define CONFIG_IDENT_STRING	" for Peach"
+
+#endif	/* __CONFIG_PEACH_PIT_H */
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 58f706a..606739b 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -1,58 +1,27 @@
 /*
  * Copyright (C) 2013 Samsung Electronics
  *
- * Configuration settings for the SAMSUNG EXYNOS5420 board.
+ * Configuration settings for the SAMSUNG SMDK5420 board.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#ifndef __CONFIG_5420_H
-#define __CONFIG_5420_H
+#ifndef __CONFIG_SMDK5420_H
+#define __CONFIG_SMDK5420_H
 
 #include <configs/exynos5-dt.h>
 
-#define CONFIG_EXYNOS5420		/* which is in a Exynos5 Family */
+#include <configs/exynos5420.h>
+
 #define CONFIG_SMDK5420			/* which is in a SMDK5420 */
 
 #undef CONFIG_DEFAULT_DEVICE_TREE
 #define CONFIG_DEFAULT_DEVICE_TREE	exynos5420-smdk5420
 
-#define CONFIG_VAR_SIZE_SPL
-
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_TEXT_BASE		0x23E00000
-
-#define CONFIG_BOARD_REV_GPIO_COUNT	2
-
-/* MACH_TYPE_SMDK5420 macro will be removed once added to mach-types */
-#define MACH_TYPE_SMDK5420		8002 /* Temporary number */
-#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5420
-
 /* select serial console configuration */
-#define CONFIG_SERIAL3			/* use SERIAL 3 */
-
-#ifdef CONFIG_VAR_SIZE_SPL
-#define CONFIG_SPL_TEXT_BASE		0x02024410
-#else
-#define CONFIG_SPL_TEXT_BASE	0x02024400
-#endif
-
-#define CONFIG_BOOTCOMMAND	"mmc read 20007000 451 2000; bootm 20007000"
-
-#define CONFIG_SYS_PROMPT		"SMDK5420 # "
-#define CONFIG_IDENT_STRING		" for SMDK5420"
-
-#define CONFIG_IRAM_TOP		0x02074000
-/*
- * Put the initial stack pointer 1KB below this to allow room for the
- * SPL marker. This value is arbitrary, but gd_t is placed starting here.
- */
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_IRAM_TOP - 0x800)
-
-#define CONFIG_MAX_I2C_NUM	11
+#define CONFIG_SERIAL3		/* use SERIAL 3 */
 
-/* Enable FIT support and comparison */
-#define CONFIG_FIT
-#define CONFIG_FIT_BEST_MATCH
+#define CONFIG_SYS_PROMPT	"SMDK5420 # "
+#define CONFIG_IDENT_STRING	" for SMDK5420"
 
-#endif	/* __CONFIG_5420_H */
+#endif	/* __CONFIG_SMDK5420_H */
