From patchwork Wed Apr 2 06:17:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jaehoon Chung X-Patchwork-Id: 336248 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id F33981400FF for ; Wed, 2 Apr 2014 17:19:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2F00C4BB20; Wed, 2 Apr 2014 08:18:54 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PlPWF1KNiY5k; Wed, 2 Apr 2014 08:18:53 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5C73F4BB21; Wed, 2 Apr 2014 08:18:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 82E924BB13 for ; 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Wed, 02 Apr 2014 15:17:41 +0900 (KST) X-AuditID: cbfee68e-b7f566d000002344-65-533bab844d2c Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id B6.B1.28157.48BAB335; Wed, 02 Apr 2014 15:17:40 +0900 (KST) Received: from localhost.localdomain ([10.252.81.186]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N3E0067R45DZT80@mmp2.samsung.com>; Wed, 02 Apr 2014 15:17:40 +0900 (KST) From: Jaehoon Chung To: u-boot@lists.denx.de Date: Wed, 02 Apr 2014 15:17:24 +0900 Message-id: <1396419451-3377-4-git-send-email-jh80.chung@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1396419451-3377-1-git-send-email-jh80.chung@samsung.com> References: <1396419451-3377-1-git-send-email-jh80.chung@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGLMWRmVeSWpSXmKPExsWyRsSkSLd1tXWwwWE1i9OftrFb3PjVxmrx 5uFmRouOIy2MFrtuT2axeLu3k92BzWPez4lMHmfv7GD06NuyijGAOYrLJiU1J7MstUjfLoEr Y9ee2+wF+4Qr9jzuY2lgfMbfxcjJISFgInGmeQ8ThC0mceHeerYuRi4OIYGljBLrVj1mgym6 M/k7M4gtJDCdUWLyh0SIojYmiSc/34Il2AR0JLZ/Ow42SURAQuJX/1VGkCJmgcmMEvN69oFN Ehbwl9g08x8LiM0ioCrx5sdWoGYODl4BV4n1d8NATAkBBYk5k2xAKjgF3CT2v2hng9jrKnGu vwfsOAmBdnaJNavvskGMEZD4NvkQC0SvrMSmA8wQN0tKHFxxg2UCo/ACRoZVjKKpBckFxUnp RUZ6xYm5xaV56XrJ+bmbGIFhfPrfs74djDcPWB9iTAYaN5FZSjQ5HxgHeSXxhsZmRhamJqbG RuaWZqQJK4nzLnqYFCQkkJ5YkpqdmlqQWhRfVJqTWnyIkYmDU6qBcfmSwxkV8XrMQhuXfte6 Y6N3ae+VrGl1p0z2vpGI3TLXNpFdseK2mBEHi+61jjsJ7uoT//ktYqhavc+8zZdhrnXxzv9q yf9FD9bM7mNbukprFU9GlOmNXPEQ+1UmkrN7G6o3NixnzmNOj31+/vzOqKTyNR5TNLRXru67 pfJ190bJNbwlD0tDlFiKMxINtZiLihMBeP/AdXkCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t9jQd2W1dbBBlfemFqc/rSN3eLGrzZW izcPNzNadBxpYbTYdXsyi8XbvZ3sDmwe835OZPI4e2cHo0ffllWMAcxRDYw2GamJKalFCql5 yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUCblRTKEnNKgUIBicXFSvp2 mCaEhrjpWsA0Ruj6hgTB9RgZoIGENYwZu/bcZi/YJ1yx53EfSwPjM/4uRk4OCQETiTuTvzND 2GISF+6tZwOxhQSmM0pM/pDYxcgFZLcxSTz5+RasiE1AR2L7t+NMILaIgITEr/6rjCBFzAKT GSXm9ewD6xYW8JfYNPMfC4jNIqAq8ebHVqBmDg5eAVeJ9XfDQEwJAQWJOZNsQCo4Bdwk9r9o h9rrKnGuv4dtAiPvAkaGVYyiqQXJBcVJ6blGesWJucWleel6yfm5mxjBcfJMegfjqgaLQ4wC HIxKPLwHzlsFC7EmlhVX5h5ilOBgVhLh5ZxkHSzEm5JYWZValB9fVJqTWnyIMRnoponMUqLJ +cAYziuJNzQ2MTOyNDI3tDAyNidNWEmc92CrdaCQQHpiSWp2ampBahHMFiYOTqkGRkvFEu2P fGdrdi8SeaxXkveQYYG6/ZEEzYdWc7/YCO1MVp2s6sNkK/WI6dDy7EvXcg4vPNPRIn+rapGu 0HY211++OhtyZmpo99sKJzYrrQwwfGASkKitwqrx53zSMb23+aFOb56f+r5hWuhF77WyBuLX VXVro75fUG7h0zw6W2bKubQDJorTlFiKMxINtZiLihMBxfODidcCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: Jaehoon Chung , panto@antoniou-consulting.com Subject: [U-Boot] [PATCHv2 03/10] ARM: exynos: clock: modify the set_mmc_clk for exynos4 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Modified the mmc_set_clock for eynos4. The goal of this patch is that fsys-div register should be reset. And retore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs) Signed-off-by: Jaehoon Chung --- arch/arm/cpu/armv7/exynos/clock.c | 16 +++++++++++----- arch/arm/include/asm/arch-exynos/clk.h | 5 +++++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 2c2029a..400d134 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int addr; + unsigned int addr, clear_bit, set_bit; /* * CLK_DIV_FSYS1 @@ -877,20 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) * CLK_DIV_FSYS2 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] * CLK_DIV_FSYS3 - * MMC4_PRE_RATIO [15:8] + * MMC4_RATIO [3:0] */ if (dev_index < 2) { addr = (unsigned int)&clk->div_fsys1; - } else if (dev_index == 4) { + clear_bit = MASK_PRE_RATIO(dev_index); + set_bit = SET_PRE_RATIO(dev_index, div); + } else if (dev_index == 4) { addr = (unsigned int)&clk->div_fsys3; dev_index -= 4; + /* MMC4 is controlled with the MMC4_RATIO value */ + clear_bit = MASK_RATIO(dev_index); + set_bit = SET_RATIO(dev_index, div); } else { addr = (unsigned int)&clk->div_fsys2; dev_index -= 2; + clear_bit = MASK_PRE_RATIO(dev_index); + set_bit = SET_PRE_RATIO(dev_index, div); } - clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), - (div & 0xff) << ((dev_index << 4) + 8)); + clrsetbits_le32(addr, clear_bit, set_bit); } /* exynos5: set the mmc clock */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index cdeef32..ffbc07e 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,11 @@ #define BPLL 5 #define RPLL 6 +#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) +#define MASK_RATIO(x) (0xf << (x << 4)) +#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8)) +#define SET_RATIO(x, y) ((y & 0xf) << (x << 4)) + enum pll_src_bit { EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL,