From patchwork Fri Mar 21 21:58:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 332772 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6B04F2C00B0 for ; Sat, 22 Mar 2014 08:58:30 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DA5D64B5F5; Fri, 21 Mar 2014 22:58:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 4G9ADB16YglU; Fri, 21 Mar 2014 22:58:26 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 09EF74B5A8; Fri, 21 Mar 2014 22:58:22 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D273B4B5A8 for ; Fri, 21 Mar 2014 22:58:18 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id iHdRMwJbnqfN for ; Fri, 21 Mar 2014 22:58:15 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from avon.wwwdotorg.org (avon.wwwdotorg.org [70.85.31.133]) by theia.denx.de (Postfix) with ESMTPS id 6FB1C4B585 for ; Fri, 21 Mar 2014 22:58:11 +0100 (CET) Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id EE5071E334; Fri, 21 Mar 2014 15:58:09 -0600 (MDT) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 5CF8AE4569; Fri, 21 Mar 2014 15:58:07 -0600 (MDT) From: Stephen Warren To: u-boot@lists.denx.de, Simon Glass , Tom Warren , Stephen Warren Date: Fri, 21 Mar 2014 15:58:03 -0600 Message-Id: <1395439083-30725-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.8.1.5 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.97.8 at avon.wwwdotorg.org X-Virus-Status: Clean Subject: [U-Boot] [PATCH] ARM: tegra: pack pinmux data tables tighter X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Stephen Warren Use smaller fields in the Tegra pinmux structures in order to pack the data tables into a smaller space. This saves around 1-3KB for the SPL and around 3-8KB for the main build of U-Boot, depending on the board, which SoC it uses, and how many pinmux table entries there are. In order to pack PMUX_FUNC_* into a smaller space, don't hard-code the values of PMUX_FUNC_RSVD* to values which require 16 bits to store them, but instead let their values be assigned automatically, so they end up fitting into 8 bits. Signed-off-by: Stephen Warren Acked-by: Simon Glass --- This depends on the previous large pinmux cleanup series I sent. arch/arm/cpu/tegra-common/pinmux-common.c | 7 +++-- arch/arm/include/asm/arch-tegra/pinmux.h | 42 ++++++++++++++--------------- arch/arm/include/asm/arch-tegra114/pinmux.h | 8 +++--- arch/arm/include/asm/arch-tegra124/pinmux.h | 8 +++--- arch/arm/include/asm/arch-tegra20/pinmux.h | 8 +++--- arch/arm/include/asm/arch-tegra30/pinmux.h | 8 +++--- 6 files changed, 40 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c index 7f7d4a87a4aa..c0b0244ddc90 100644 --- a/arch/arm/cpu/tegra-common/pinmux-common.c +++ b/arch/arm/cpu/tegra-common/pinmux-common.c @@ -14,8 +14,7 @@ /* return 1 if a pmux_func is in range */ #define pmux_func_isvalid(func) \ - ((((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) || \ - (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4))) + (((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) /* return 1 if a pin_pupd_is in range */ #define pmux_pin_pupd_isvalid(pupd) \ @@ -101,8 +100,8 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) assert(pmux_pingrp_isvalid(pin)); assert(pmux_func_isvalid(func)); - if (func & PMUX_FUNC_RSVD1) { - mux = func & 3; + if (func >= PMUX_FUNC_RSVD1) { + mux = (func - PMUX_FUNC_RSVD1) & 3; } else { /* Search for the appropriate function */ for (i = 0; i < 4; i++) { diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 80b804694aee..035159d66537 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -64,18 +64,18 @@ enum pmux_pin_rcv_sel { * available is pinmux_config_table() to configure a list of pins. */ struct pmux_pingrp_config { - enum pmux_pingrp pingrp; /* pin group PMUX_PINGRP_... */ - enum pmux_func func; /* function to assign PMUX_FUNC_... */ - enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ - enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ + u32 pingrp:16; /* pin group PMUX_PINGRP_... */ + u32 func:8; /* function to assign PMUX_FUNC_... */ + u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ + u32 tristate:2; /* tristate or normal PMUX_TRI_... */ #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC - enum pmux_pin_io io; /* input or output PMUX_PIN_... */ - enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */ - enum pmux_pin_od od; /* open-drain or push-pull driver */ - enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */ + u32 io:2; /* input or output PMUX_PIN_... */ + u32 lock:2; /* lock enable/disable PMUX_PIN... */ + u32 od:2; /* open-drain or push-pull driver */ + u32 ioreset:2; /* input/output reset PMUX_PIN... */ #ifdef TEGRA_PMX_HAS_RCV_SEL - enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */ - /* VIL/VIH receivers */ + u32 rcv_sel:2; /* select between High and Normal */ + /* VIL/VIH receivers */ #endif #endif }; @@ -151,14 +151,14 @@ enum pmux_hsm { * This defines the configuration for a pin group's pad control config */ struct pmux_drvgrp_config { - enum pmux_drvgrp drvgrp; /* pin group PMUX_DRVGRP_x */ - int slwf; /* falling edge slew */ - int slwr; /* rising edge slew */ - int drvup; /* pull-up drive strength */ - int drvdn; /* pull-down drive strength */ - enum pmux_lpmd lpmd; /* low-power mode selection */ - enum pmux_schmt schmt; /* schmidt enable */ - enum pmux_hsm hsm; /* high-speed mode enable */ + u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ + u32 slwf:3; /* falling edge slew */ + u32 slwr:3; /* rising edge slew */ + u32 drvup:8; /* pull-up drive strength */ + u32 drvdn:8; /* pull-down drive strength */ + u32 lpmd:3; /* low-power mode selection */ + u32 schmt:2; /* schmidt enable */ + u32 hsm:2; /* high-speed mode enable */ }; /** @@ -173,10 +173,10 @@ void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, #endif /* TEGRA_PMX_HAS_DRVGRPS */ struct pmux_pingrp_desc { - enum pmux_func funcs[4]; + u8 funcs[4]; #if defined(CONFIG_TEGRA20) - u32 ctl_id; - u32 pull_id; + u8 ctl_id; + u8 pull_id; #endif /* CONFIG_TEGRA20 */ }; diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 0df69e3ab34b..c1cb3ef16b1a 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -305,11 +305,11 @@ enum pmux_func { PMUX_FUNC_VI, PMUX_FUNC_VI_ALT1, PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, PMUX_FUNC_COUNT, - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, }; #define TEGRA_PMX_HAS_PIN_IO_BIT_ETC diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 70254b5c731e..c49801c21d07 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -327,11 +327,11 @@ enum pmux_func { PMUX_FUNC_VI_ALT3, PMUX_FUNC_VIMCLK2, PMUX_FUNC_VIMCLK2_ALT, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, PMUX_FUNC_COUNT, - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, }; #define TEGRA_PMX_HAS_PIN_IO_BIT_ETC diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index d7802d967597..11c0104ff3e0 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -225,11 +225,11 @@ enum pmux_func { PMUX_FUNC_VI, PMUX_FUNC_VI_SENSOR_CLK, PMUX_FUNC_XIO, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, PMUX_FUNC_COUNT, - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, }; #include diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 3fed194339dd..6d83061dc1e9 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -383,11 +383,11 @@ enum pmux_func { PMUX_FUNC_VI_ALT1, PMUX_FUNC_VI_ALT2, PMUX_FUNC_VI_ALT3, + PMUX_FUNC_RSVD1, + PMUX_FUNC_RSVD2, + PMUX_FUNC_RSVD3, + PMUX_FUNC_RSVD4, PMUX_FUNC_COUNT, - PMUX_FUNC_RSVD1 = 0x8000, - PMUX_FUNC_RSVD2 = 0x8001, - PMUX_FUNC_RSVD3 = 0x8002, - PMUX_FUNC_RSVD4 = 0x8003, }; #define TEGRA_PMX_HAS_PIN_IO_BIT_ETC