diff mbox

[U-Boot] axs101: flush DMA buffer descriptors before DMA transactons starts

Message ID 1395406667-25009-1-git-send-email-abrodkin@synopsys.com
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Alexey Brodkin March 21, 2014, 12:57 p.m. UTC 
CPU sets DMA buffer descriptors with data required for inetrnal DMA such as:
 * Ownership of BD
 * Buffer size
 * Pointer to data buffer in memory

Then we need to make sure DMA engine of NAND controller gets proper data.
For this we flush buffer rescriptor.

Then we're  ready for DMA transaction.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Tom Rini <trini@ti.com>
---
 board/synopsys/axs101/nand.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Tom Rini March 28, 2014, 9:16 p.m. UTC | #1 
On Fri, Mar 21, 2014 at 04:57:47PM +0400, Alexey Brodkin wrote:

> CPU sets DMA buffer descriptors with data required for inetrnal DMA such as:
>  * Ownership of BD
>  * Buffer size
>  * Pointer to data buffer in memory
> 
> Then we need to make sure DMA engine of NAND controller gets proper data.
> For this we flush buffer rescriptor.
> 
> Then we're  ready for DMA transaction.
> 
> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c
index 8672803..c7f90c4 100644
--- a/board/synopsys/axs101/nand.c
+++ b/board/synopsys/axs101/nand.c
@@ -107,6 +107,10 @@  static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
 	writel(0, &bd->buffer_ptr1);
 
+	/* Flush modified buffer descriptor */
+	flush_dcache_range((unsigned long)bd,
+			   (unsigned long)bd + sizeof(struct nand_bd));
+
 	/* Issue "write" command */
 	NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
 
@@ -137,6 +141,10 @@  static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 	writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
 	writel(0, &bd->buffer_ptr1);
 
+	/* Flush modified buffer descriptor */
+	flush_dcache_range((unsigned long)bd,
+			   (unsigned long)bd + sizeof(struct nand_bd));
+
 	/* Issue "read" command */
 	NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));