Message ID | 1390756001-11127-2-git-send-email-festevam@gmail.com |
---|---|
State | Accepted |
Delegated to: | Stefano Babic |
Headers | show |
Hi Fabio, On 26/01/2014 18:06, Fabio Estevam wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > Currently when we boot a mx6dual U-boot reports that it is a mx6quad. > > Report it as MX6D instead: > > CPU: Freescale i.MX6D rev1.2 at 792 MHz > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > Changes since v3: > - Fix From field > Changes since v2: > - use a common cpu.h header > > arch/arm/cpu/armv7/mx6/soc.c | 14 +++++++++++--- > arch/arm/imx-common/cpu.c | 2 ++ > arch/arm/include/asm/arch-imx/cpu.h | 1 + > 3 files changed, 14 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index 0208cba..9acd8c9 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -41,14 +41,19 @@ u32 get_cpu_rev(void) > > if (type != MXC_CPU_MX6SL) { > reg = readl(&anatop->digprog); > + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; > + u32 cfg = readl(&scu->config) & 3; > type = ((reg >> 16) & 0xff); > if (type == MXC_CPU_MX6DL) { > - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; > - u32 cfg = readl(&scu->config) & 3; > - > if (!cfg) > type = MXC_CPU_MX6SOLO; > } > + > + if (type == MXC_CPU_MX6Q) { > + if (cfg == 1) > + type = MXC_CPU_MX6D; > + } > + > } > reg &= 0xff; /* mx6 silicon revision */ > return (type << 12) | (reg + 0x10); > @@ -62,6 +67,9 @@ u32 __weak get_board_rev(void) > if (type == MXC_CPU_MX6SOLO) > cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); > > + if (type == MXC_CPU_MX6D) > + cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); > + > return cpurev; > } > #endif > diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c > index 9231649..a77c4de 100644 > --- a/arch/arm/imx-common/cpu.c > +++ b/arch/arm/imx-common/cpu.c > @@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype) > switch (imxtype) { > case MXC_CPU_MX6Q: > return "6Q"; /* Quad-core version of the mx6 */ > + case MXC_CPU_MX6D: > + return "6D"; /* Dual-core version of the mx6 */ > case MXC_CPU_MX6DL: > return "6DL"; /* Dual Lite version of the mx6 */ > case MXC_CPU_MX6SOLO: > diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h > index 8c725e2..a35940e 100644 > --- a/arch/arm/include/asm/arch-imx/cpu.h > +++ b/arch/arm/include/asm/arch-imx/cpu.h > @@ -10,3 +10,4 @@ > #define MXC_CPU_MX6DL 0x61 > #define MXC_CPU_MX6SOLO 0x62 > #define MXC_CPU_MX6Q 0x63 > +#define MXC_CPU_MX6D 0x64 > Acked-by: Stefano babic <sbabic@denx.de> Best regards, Stefano Babic
On Sun, Jan 26, 2014 at 8:39 PM, Stefano Babic <sbabic@denx.de> wrote: > Hi Fabio, > > > On 26/01/2014 18:06, Fabio Estevam wrote: >> >> From: Fabio Estevam <fabio.estevam@freescale.com> >> >> Currently when we boot a mx6dual U-boot reports that it is a mx6quad. >> >> Report it as MX6D instead: >> >> CPU: Freescale i.MX6D rev1.2 at 792 MHz >> >> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> >> --- >> Changes since v3: >> - Fix From field >> Changes since v2: >> - use a common cpu.h header >> >> arch/arm/cpu/armv7/mx6/soc.c | 14 +++++++++++--- >> arch/arm/imx-common/cpu.c | 2 ++ >> arch/arm/include/asm/arch-imx/cpu.h | 1 + >> 3 files changed, 14 insertions(+), 3 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c >> index 0208cba..9acd8c9 100644 >> --- a/arch/arm/cpu/armv7/mx6/soc.c >> +++ b/arch/arm/cpu/armv7/mx6/soc.c >> @@ -41,14 +41,19 @@ u32 get_cpu_rev(void) >> >> if (type != MXC_CPU_MX6SL) { >> reg = readl(&anatop->digprog); >> + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; >> + u32 cfg = readl(&scu->config) & 3; >> type = ((reg >> 16) & 0xff); >> if (type == MXC_CPU_MX6DL) { >> - struct scu_regs *scu = (struct scu_regs >> *)SCU_BASE_ADDR; >> - u32 cfg = readl(&scu->config) & 3; >> - >> if (!cfg) >> type = MXC_CPU_MX6SOLO; >> } >> + >> + if (type == MXC_CPU_MX6Q) { >> + if (cfg == 1) >> + type = MXC_CPU_MX6D; >> + } >> + >> } >> reg &= 0xff; /* mx6 silicon revision */ >> return (type << 12) | (reg + 0x10); >> @@ -62,6 +67,9 @@ u32 __weak get_board_rev(void) >> if (type == MXC_CPU_MX6SOLO) >> cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); >> >> + if (type == MXC_CPU_MX6D) >> + cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); >> + >> return cpurev; >> } >> #endif >> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c >> index 9231649..a77c4de 100644 >> --- a/arch/arm/imx-common/cpu.c >> +++ b/arch/arm/imx-common/cpu.c >> @@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype) >> switch (imxtype) { >> case MXC_CPU_MX6Q: >> return "6Q"; /* Quad-core version of the mx6 */ >> + case MXC_CPU_MX6D: >> + return "6D"; /* Dual-core version of the mx6 */ >> case MXC_CPU_MX6DL: >> return "6DL"; /* Dual Lite version of the mx6 */ >> case MXC_CPU_MX6SOLO: >> diff --git a/arch/arm/include/asm/arch-imx/cpu.h >> b/arch/arm/include/asm/arch-imx/cpu.h >> index 8c725e2..a35940e 100644 >> --- a/arch/arm/include/asm/arch-imx/cpu.h >> +++ b/arch/arm/include/asm/arch-imx/cpu.h >> @@ -10,3 +10,4 @@ >> #define MXC_CPU_MX6DL 0x61 >> #define MXC_CPU_MX6SOLO 0x62 >> #define MXC_CPU_MX6Q 0x63 >> +#define MXC_CPU_MX6D 0x64 >> > > Acked-by: Stefano babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
On 26/01/2014 18:06, Fabio Estevam wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > Currently when we boot a mx6dual U-boot reports that it is a mx6quad. > > Report it as MX6D instead: > > CPU: Freescale i.MX6D rev1.2 at 792 MHz > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 0208cba..9acd8c9 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -41,14 +41,19 @@ u32 get_cpu_rev(void) if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; type = ((reg >> 16) & 0xff); if (type == MXC_CPU_MX6DL) { - struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; - u32 cfg = readl(&scu->config) & 3; - if (!cfg) type = MXC_CPU_MX6SOLO; } + + if (type == MXC_CPU_MX6Q) { + if (cfg == 1) + type = MXC_CPU_MX6D; + } + } reg &= 0xff; /* mx6 silicon revision */ return (type << 12) | (reg + 0x10); @@ -62,6 +67,9 @@ u32 __weak get_board_rev(void) if (type == MXC_CPU_MX6SOLO) cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); + if (type == MXC_CPU_MX6D) + cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); + return cpurev; } #endif diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 9231649..a77c4de 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype) switch (imxtype) { case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ + case MXC_CPU_MX6D: + return "6D"; /* Dual-core version of the mx6 */ case MXC_CPU_MX6DL: return "6DL"; /* Dual Lite version of the mx6 */ case MXC_CPU_MX6SOLO: diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 8c725e2..a35940e 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -10,3 +10,4 @@ #define MXC_CPU_MX6DL 0x61 #define MXC_CPU_MX6SOLO 0x62 #define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6D 0x64