From patchwork Thu Dec 19 03:16:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 303151 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CFE2B2C0089 for ; Thu, 19 Dec 2013 14:17:34 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 74AD14A29C; Thu, 19 Dec 2013 04:17:33 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lPQNfAk9ayU9; Thu, 19 Dec 2013 04:17:33 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9980B4A08B; Thu, 19 Dec 2013 04:17:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 506C14A08F for ; Thu, 19 Dec 2013 04:17:09 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id K8A8DNHuPuD8 for ; Thu, 19 Dec 2013 04:17:04 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from mail-yh0-f53.google.com (mail-yh0-f53.google.com [209.85.213.53]) by theia.denx.de (Postfix) with ESMTPS id 12A734A065 for ; Thu, 19 Dec 2013 04:16:56 +0100 (CET) Received: by mail-yh0-f53.google.com with SMTP id b20so190152yha.26 for ; Wed, 18 Dec 2013 19:16:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/boVmd3J00JKbgi/fUtx8WOpCMFP7VwHop6MAIlSxGM=; b=B+sHAWHx8SeBg4DJpzRT4sH1uBdRLAZnW/jWSgI99LCCJ3CUFbjtRibYQ4QWshHa+T Zbzg0LdtzyMOJ5zoY/J3fvY7N7Qx3H1QWZS32QAAsChWz0zLnzJ15SMN0xhdVvSwMBVA wcnP41U9PGBR9BCQOm+QhfL0t7sEMeMKk+Rn6/Zl0u+7VLMrS6uCUHJE2mcXQYgyy+Bh OfBuJGoZNnGtYjOSbd/rPb5P7SFEb2GvY0isbkR4+US58Ye70mrn6ccqFDNLJk9Dt84r s/fgJEFPY2qCJ5rc+7DKvna7LbM3a0bfMRhrgVv9ONZAnuF/9fTH3km2UUsPy/lVHxQx R9Mg== X-Received: by 10.236.147.107 with SMTP id s71mr25203329yhj.45.1387423015504; Wed, 18 Dec 2013 19:16:55 -0800 (PST) Received: from localhost.localdomain ([177.194.40.144]) by mx.google.com with ESMTPSA id n48sm3848129yho.24.2013.12.18.19.16.53 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 18 Dec 2013 19:16:55 -0800 (PST) From: Fabio Estevam To: sbabic@denx.de Date: Thu, 19 Dec 2013 01:16:29 -0200 Message-Id: <1387422989-15307-6-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1387422989-15307-1-git-send-email-festevam@gmail.com> References: <1387422989-15307-1-git-send-email-festevam@gmail.com> Cc: Fabio Estevam , u-boot@lists.denx.de, RA5478@freescale.com, b20788@freescale.com Subject: [U-Boot] [PATCH 6/6] mx6: soc: Disable VDDPU regulator X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator in order to save power. Signed-off-by: Anson Huang Signed-off-by: Jason Liu Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx6/soc.c | 23 +++++++++++++++++++++++ arch/arm/include/asm/arch-mx6/imx-regs.h | 23 +++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 9dc30ba..243226e 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -19,6 +19,8 @@ #include #include +#define VDDPU_MASK (0x1f << 9) + enum ldo_reg { LDO_ARM, LDO_SOC, @@ -177,11 +179,32 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } +static void imx_set_vddpu_power_down(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR; + + u32 val; + + /* need to power down xPU in GPC before turning off PU LDO */ + val = readl(&gpc->gpu_ctrl); + writel(val | 0x1, &gpc->gpu_ctrl); + + val = readl(&gpc->ctrl); + writel(val | 0x1, &gpc->ctrl); + while (readl(&gpc->ctrl) & 0x1) + ; + + /* disable VDDPU */ + writel(VDDPU_MASK, &anatop->reg_core_clr); +} + int arch_cpu_init(void) { init_aips(); imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ + imx_set_vddpu_power_down(); #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 7ef7152..fb0c4c7 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -659,5 +659,28 @@ struct wdog_regs { u16 wmcr; /* Miscellaneous Control */ }; +struct gpc_regs { + u32 ctrl; /* 0x000 */ + u32 pgr; /* 0x004 */ + u32 imr1; /* 0x008 */ + u32 imr2; /* 0x00c */ + u32 imr3; /* 0x010 */ + u32 imr4; /* 0x014 */ + u32 isr1; /* 0x018 */ + u32 isr2; /* 0x01c */ + u32 isr3; /* 0x020 */ + u32 isr4; /* 0x024 */ + u32 reserved1[0x86]; + u32 gpu_ctrl; /* 0x260 */ + u32 gpu_pupscr; /* 0x264 */ + u32 gpu_pdnscr; /* 0x268 */ + u32 gpu_sr; /* 0x26c */ + u32 reserved2[0xc]; + u32 cpu_ctrl; /* 0x2a0 */ + u32 cpu_pupscr; /* 0x2a4 */ + u32 cpu_pdnscr; /* 0x2a8 */ + u32 cpu_sr; /* 0x2ac */ +}; + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */