From patchwork Wed Dec 18 22:23:35 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin Liang See X-Patchwork-Id: 303101 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 8B4022C009B for ; Thu, 19 Dec 2013 09:24:08 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 32D8E4A978; Wed, 18 Dec 2013 23:24:06 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6t13orQjDw98; Wed, 18 Dec 2013 23:24:06 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C3AEB4A17A; Wed, 18 Dec 2013 23:24:02 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4C0E14A17A for ; Wed, 18 Dec 2013 23:23:56 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aO3gbu30RekU for ; Wed, 18 Dec 2013 23:23:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=SKIP(-1.5) (only DNSBL check requested) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe001.messaging.microsoft.com [207.46.163.24]) by theia.denx.de (Postfix) with ESMTPS id 099C44A080 for ; Wed, 18 Dec 2013 23:23:48 +0100 (CET) Received: from mail51-co9-R.bigfish.com (10.236.132.253) by CO9EHSOBE031.bigfish.com (10.236.130.94) with Microsoft SMTP Server id 14.1.225.22; Wed, 18 Dec 2013 22:23:47 +0000 Received: from mail51-co9 (localhost [127.0.0.1]) by mail51-co9-R.bigfish.com (Postfix) with ESMTP id 374FB4C0230; Wed, 18 Dec 2013 22:23:47 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.231; KIP:(null); UIP:(null); IPV:NLI; H:sj-itexedge01.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah1fc6hzz8275ch1de098h8275bh1de097hz2fh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah224fh1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1fe8h1ff5h2218h2216h226dh22d0h2327h2336h1155h) Received-SPF: pass (mail51-co9: domain of altera.com designates 66.35.236.231 as permitted sender) client-ip=66.35.236.231; envelope-from=clsee@altera.com; helo=sj-itexedge01.altera.priv.altera.com ; v.altera.com ; Received: from mail51-co9 (localhost.localdomain [127.0.0.1]) by mail51-co9 (MessageSwitch) id 1387405425157877_22069; Wed, 18 Dec 2013 22:23:45 +0000 (UTC) Received: from CO9EHSMHS028.bigfish.com (unknown [10.236.132.231]) by mail51-co9.bigfish.com (Postfix) with ESMTP id 17C85C0004A; Wed, 18 Dec 2013 22:23:45 +0000 (UTC) Received: from sj-itexedge01.altera.priv.altera.com (66.35.236.231) by CO9EHSMHS028.bigfish.com (10.236.130.38) with Microsoft SMTP Server (TLS) id 14.16.227.3; Wed, 18 Dec 2013 22:23:44 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by sj-itexedge01.altera.priv.altera.com (66.35.236.231) with Microsoft SMTP Server id 8.3.298.1; Wed, 18 Dec 2013 14:15:11 -0800 Received: from clsee-VirtualBox.altera.com (tx-clsee-530.altera.priv.altera.com [137.57.188.152]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id rBIMNaVe001632; Wed, 18 Dec 2013 14:23:43 -0800 (PST) From: Chin Liang See To: ZY - u-boot Date: Wed, 18 Dec 2013 16:23:35 -0600 Message-ID: <1387405415-4519-1-git-send-email-clsee@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Chin Liang See , Tom@theia.denx.de, Rini Subject: [U-Boot] [PATCH] watchdog/denali: Adding DesignWare watchdog driver support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: Chin Liang See Cc: Anatolij Gustschin Cc: Albert Aribaud Cc: Heiko Schocher Cc: Tom Rini --- drivers/watchdog/Makefile | 1 + drivers/watchdog/designware_wdt.c | 75 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 drivers/watchdog/designware_wdt.c diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 06ced10..0276a10 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o +obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o diff --git a/drivers/watchdog/designware_wdt.c b/drivers/watchdog/designware_wdt.c new file mode 100644 index 0000000..c3b14f5 --- /dev/null +++ b/drivers/watchdog/designware_wdt.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define DW_WDT_CR 0x00 +#define DW_WDT_TORR 0x04 +#define DW_WDT_CRR 0x0C + +#define DW_WDT_CR_EN_OFFSET 0x00 +#define DW_WDT_CR_RMOD_OFFSET 0x01 +#define DW_WDT_CR_RMOD_VAL 0x00 +#define DW_WDT_CRR_RESTART_VAL 0x76 + +/* + * Set the watchdog time interval. + * Counter is 32 bit. + */ +int designware_wdt_settimeout(unsigned int timeout) +{ + signed int i; + /* calculate the timeout range value */ + i = (log_2_n_round_up(timeout * CONFIG_DW_WDT_CLOCK_KHZ))\ + - 16; + if (i > 15) + i = 15; + if (i < 0) + i = 0; + + writel((i | (i<<4)), + (CONFIG_DW_WDT_BASE + DW_WDT_TORR)); + return 0; +} + +void designware_wdt_enable(void) +{ + writel(((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) | \ + (0x1 << DW_WDT_CR_EN_OFFSET)), + (CONFIG_DW_WDT_BASE + DW_WDT_CR)); +} + +unsigned int designware_wdt_is_enabled(void) +{ + unsigned long val; + val = readl((CONFIG_DW_WDT_BASE + DW_WDT_CR)); + return val & 0x1; +} + +#if defined(CONFIG_HW_WATCHDOG) +void hw_watchdog_reset(void) +{ + if (designware_wdt_is_enabled()) + /* restart the watchdog counter */ + writel(DW_WDT_CRR_RESTART_VAL, + (CONFIG_DW_WDT_BASE + DW_WDT_CRR)); +} + +void hw_watchdog_init(void) +{ + /* reset to disable the watchdog */ + hw_watchdog_reset(); + /* set timer in miliseconds */ + designware_wdt_settimeout(CONFIG_HW_WATCHDOG_TIMEOUT_MS); + /* enable the watchdog */ + designware_wdt_enable(); + /* reset the watchdog */ + hw_watchdog_reset(); +} +#endif