[U-Boot,4/5] ARM: OMAP5: Add SATA platform glue

diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 6e4a0f0..0535b62 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -23,6 +23,9 @@  endif
 
 ifneq ($(CONFIG_OMAP54XX),)
 COBJS	+= pipe3-phy.o
+ifdef CONFIG_SCSI_AHCI_PLAT
+COBJS	+= sata.o
+endif
 endif
 
 ifeq ($(CONFIG_OMAP34XX),)
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
new file mode 100644
index 0000000..eb079c3
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -0,0 +1,78 @@ 
+/*
+ * TI SATA platform driver
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sata.h>
+#include <asm/io.h>
+#include "pipe3-phy.h"
+
+#if defined(CONFIG_SCSI_AHCI_PLAT)
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+	{12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
+	{16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
+	{19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
+	{20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
+	{26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
+	{38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
+	{ },                                    /* Terminator */
+};
+
+struct omap_pipe3 sata_phy = {
+	.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
+	/* .power_reg is updated at runtime */
+	.dpll_map = dpll_map_sata,
+};
+
+int omap_sata_init(void)
+{
+	int ret;
+	u32 val;
+
+	u32 const clk_domains_sata[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_sata[] = {
+		(*prcm)->cm_l3init_ocp2scp3_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_sata[] = {
+		(*prcm)->cm_l3init_sata_clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_sata,
+			clk_modules_hw_auto_sata,
+			clk_modules_explicit_en_sata,
+			0);
+
+	/* Enable optional functional clock for SATA */
+	setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+			SATA_CLKCTRL_OPTFCLKEN_MASK);
+
+	sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
+
+	/* Power up the PHY */
+	phy_pipe3_power_on(&sata_phy);
+
+	/* Enable SATA module, No Idle, No Standby */
+	val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
+	writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
+
+	ret = ahci_init(DWC_AHSATA_BASE);
+	scsi_scan(1);
+
+	return ret;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h
new file mode 100644
index 0000000..2ca8947
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sata.h
@@ -0,0 +1,48 @@ 
+/*
+ * SATA Wrapper Register map
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TI_SATA_H
+#define _TI_SATA_H
+
+/* SATA Wrapper module */
+#define TI_SATA_WRAPPER_BASE		(OMAP54XX_L4_CORE_BASE + 0x141100)
+/* SATA PHY Module */
+#define TI_SATA_PLLCTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x96800)
+
+/* SATA Wrapper register offsets */
+#define TI_SATA_SYSCONFIG			0x00
+#define TI_SATA_CDRLOCK				0x04
+
+/* Register Set */
+#define TI_SATA_SYSCONFIG_OVERRIDE0		(1 << 16)
+#define TI_SATA_SYSCONFIG_STANDBY_MASK		(0x3 << 4)
+#define TI_SATA_SYSCONFIG_IDLE_MASK		(0x3 << 2)
+
+/* Standby modes */
+#define TI_SATA_STANDBY_FORCE			0x0
+#define TI_SATA_STANDBY_NO			(0x1 << 4)
+#define TI_SATA_STANDBY_SMART_WAKE		(0x3 << 4)
+#define TI_SATA_STANDBY_SMART			(0x2 << 4)
+
+/* Idle modes */
+#define TI_SATA_IDLE_FORCE			0x0
+#define TI_SATA_IDLE_NO				(0x1 << 2)
+#define TI_SATA_IDLE_SMART_WAKE			(0x3 << 2)
+#define TI_SATA_IDLE_SMART			(0x2 << 2)
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int omap_sata_init(void);
+#else
+static inline int omap_sata_init(void)
+{
+	return 0;
+}
+#endif /* CONFIG_SCSI_AHCI_PLAT */
+
+#endif /* _TI_SATA_H */