From patchwork Mon Sep 30 01:30:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 278900 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 90FB02C00BA for ; Mon, 30 Sep 2013 11:32:03 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8288E4A0AB; Mon, 30 Sep 2013 03:31:49 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Q5wF8n2wW6ow; Mon, 30 Sep 2013 03:31:49 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 559574A097; Mon, 30 Sep 2013 03:31:25 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CEE674A0A1 for ; Mon, 30 Sep 2013 03:31:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id C8lCDfy38r5Q for ; Mon, 30 Sep 2013 03:31:10 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pa0-f52.google.com (mail-pa0-f52.google.com [209.85.220.52]) by theia.denx.de (Postfix) with ESMTPS id 4D32C4A081 for ; Mon, 30 Sep 2013 03:31:04 +0200 (CEST) Received: by mail-pa0-f52.google.com with SMTP id kl14so5120366pab.25 for ; Sun, 29 Sep 2013 18:30:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=HUCUjC7LX6YiJY0f7wXoKhzvxX254s56W0nyFG8otgc=; b=gmNavjlSScfW/l62SGzBj33CHuRmLlj2t9QBwSytXPDudSPtAmZbUc4MlLAWXYysnS fa7rs+RRZkTdDXhIiaSQ6EHovMEri/HGqF584+kjQslnYarHEhBL6kC7HXKMILO0k025 ESM27WCPpMnazcgfiuKReIlghszlNZ1OrlBg/WojkzsrirxWGzz1db95iFoCCmRgf6+N QxrEURAAJ/Y/rlySDoKejMrk+jviylAdZKrgwrrPPbOMOTWTdD7h7TqiUD1PIfcx7VvB o84PAaZg6ldBecNkVHTFjKRyC2g/LYra1h4asqpc23UeAAM5QVNpO9Xs0UK4Y8BEWOmg 325g== X-Gm-Message-State: ALoCoQnNe7jjihezC58dd049IDNCyZCIyAApAp9VfTCr902sindOC0flmgjqiqwaZR0DIjI62XcW X-Received: by 10.68.191.102 with SMTP id gx6mr193071pbc.161.1380504658156; Sun, 29 Sep 2013 18:30:58 -0700 (PDT) Received: from xps-iwamatsu.renesas.com (49.14.32.202.bf.2iij.net. [202.32.14.49]) by mx.google.com with ESMTPSA id gh2sm23199896pbc.40.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 29 Sep 2013 18:30:57 -0700 (PDT) From: Nobuhiro Iwamatsu To: u-boot@lists.denx.de Date: Mon, 30 Sep 2013 10:30:40 +0900 Message-Id: <1380504641-11469-3-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> X-Mailer: git-send-email 1.8.4.rc3 In-Reply-To: <1380504641-11469-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> References: <1380504641-11469-1-git-send-email-nobuhiro.iwamatsu.yj@renesas.com> Cc: Nobuhiro Iwamatsu Subject: [U-Boot] [PATCH v2 3/4] arm: rmobile: kzm9g: Change clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Nobuhiro Iwamatsu CC: Nobuhiro Iwamatsu CC: Albert Aribaud --- v2: no changes. re-send as further series. include/configs/kzm9g.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 222725c..6323050 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -125,6 +125,7 @@ #define CONFIG_GLOBAL_TIMER #define CONFIG_SYS_CLK_FREQ (48000000) #define CONFIG_SYS_CPU_CLK (1196000000) +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CFG_HZ (1000) #define CONFIG_SYS_HZ CFG_HZ