From patchwork Tue Jul 2 03:52:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Priyanka Jain X-Patchwork-Id: 256263 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B668A2C00A6 for ; Tue, 2 Jul 2013 13:52:58 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EF7B94A14A; Tue, 2 Jul 2013 05:52:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t-saXKEr6PC9; Tue, 2 Jul 2013 05:52:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 898074A157; Tue, 2 Jul 2013 05:52:52 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EC5BE4A157 for ; Tue, 2 Jul 2013 05:52:45 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HB2wgfLDcWJ7 for ; Tue, 2 Jul 2013 05:52:41 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from db8outboundpool.messaging.microsoft.com (mail-db8lp0185.outbound.messaging.microsoft.com [213.199.154.185]) by theia.denx.de (Postfix) with ESMTPS id 1F0414A14A for ; Tue, 2 Jul 2013 05:52:35 +0200 (CEST) Received: from mail192-db8-R.bigfish.com (10.174.8.226) by DB8EHSOBE013.bigfish.com (10.174.4.76) with Microsoft SMTP Server id 14.1.225.23; Tue, 2 Jul 2013 03:52:34 +0000 Received: from mail192-db8 (localhost [127.0.0.1]) by mail192-db8-R.bigfish.com (Postfix) with ESMTP id 6EE85C00E9 for ; Tue, 2 Jul 2013 03:52:34 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 1 X-BigFish: VS1(z551bizzz1f42h1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e23h1155h) Received: from mail192-db8 (localhost.localdomain [127.0.0.1]) by mail192-db8 (MessageSwitch) id 137273715361968_2723; Tue, 2 Jul 2013 03:52:33 +0000 (UTC) Received: from DB8EHSMHS028.bigfish.com (unknown [10.174.8.241]) by mail192-db8.bigfish.com (Postfix) with ESMTP id 02217400049 for ; Tue, 2 Jul 2013 03:52:33 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS028.bigfish.com (10.174.4.38) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 2 Jul 2013 03:52:33 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.328.11; Tue, 2 Jul 2013 03:52:30 +0000 Received: from b32167-VirtualBox.ap.freescale.net (B32167-02-010232014010.ap.freescale.net [10.232.14.10]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r623qPVg028499; Mon, 1 Jul 2013 20:52:29 -0700 From: Priyanka Jain To: Date: Tue, 2 Jul 2013 09:22:23 +0530 Message-ID: <1372737143-2080-1-git-send-email-Priyanka.Jain@freescale.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: scottwood@freescale.com, Priyanka Jain , afleming@zil05.freescale.net Subject: [U-Boot] [PATCH 2/2][v2] board/bsc9132qds: Configure DSP DDR controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi Signed-off-by: Priyanka Jain --- Changes for v2: Added Manish's email-id arch/powerpc/include/asm/immap_85xx.h | 6 ++++++ board/freescale/bsc9132qds/bsc9132qds.c | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index db70d04..ae9a016 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3047,6 +3047,12 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 +#if defined(CONFIG_BSC9132) +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 +#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ + (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) +#endif + #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index ddc9d0a..b084c1b 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -141,6 +141,27 @@ void board_config_serdes_mux(void) } } +/* Configure DSP DDR controller */ +void dsp_ddr_configure(void) +{ + /* + *There are separate DDR-controllers for DSP and PowerPC side DDR. + *copy the ddr controller settings from PowerPC side DDR controller + *to the DSP DDR controller as connected DDR memories are similar. + */ + ccsr_ddr_t __iomem *pa_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t temp_ddr; + ccsr_ddr_t __iomem *dsp_ddr = + (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; + + memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t)); + temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; + temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; + memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t)); + dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; +} + int board_early_init_r(void) { #ifndef CONFIG_SYS_NO_FLASH @@ -169,6 +190,7 @@ int board_early_init_r(void) 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); #endif board_config_serdes_mux(); + dsp_ddr_configure(); return 0; }