diff --git a/README b/README
index 862bb3e..f974bca 100644
--- a/README
+++ b/README
@@ -2887,6 +2887,10 @@ FIT uImage format:
 		CONFIG_SPL_INIT_MINIMAL
 		Arch init code should be built for a very small image
 
+		CONFIG_SPL_INIT_NORMAL
+		This is relative to MINIMAL, this init code contains some
+		features that the minimal SPL doesn't contains.
+
 		CONFIG_SPL_LIBCOMMON_SUPPORT
 		Support for common/libcommon.o in SPL binary
 
@@ -2977,6 +2981,21 @@ FIT uImage format:
 		CONFIG_SPL_LIBGENERIC_SUPPORT
 		Support for lib/libgeneric.o in SPL binary
 
+		CONFIG_SPL_INIT_DDR_SUPPORT
+		Support for common DDR init in SPL binary
+
+		CONFIG_SPL_HWCONFIG_SUPPORT
+		Support for configuring hardware via environment in SPL binary
+
+		CONFIG_SPL_ENV_SUPPORT
+		Support for the environment operating in SPL binary
+
+		CONFIG_SPL_ADDR_MAP_SUPPORT
+		Support for mutual transformation between virtual addr to CPU bus addr
+
+		CONFIG_SPL_UTILITYLIB_SUPPORT
+		Support for some common tools in SPL binary, such as: hashtable
+
 		CONFIG_SPL_PAD_TO
 		Image offset to which the SPL should be padded before appending
 		the SPL payload. By default, this is defined as
@@ -3965,6 +3984,11 @@ Low Level (hardware related) configuration options:
 		that is executed before the actual U-Boot. E.g. when
 		compiling a NAND SPL.
 
+- CONFIG_SYS_MPC85XX_NO_RESETVEC
+		Only for 85xx systems. If this variable is specified, the section
+		.resetvec is not kept and the section .bootpg is placed in the
+		previous 4k of the .text section.
+
 - CONFIG_ARCH_MAP_SYSMEM
 		Generally U-Boot (and in particular the md command) uses
 		effective address. It is therefore not necessary to regard
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 0dff37f..d21b324 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -55,7 +55,7 @@ void init_tlbs(void)
 	return ;
 }
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD_MINIMAL)
 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
 		       phys_addr_t *rpn)
 {
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index f2b7bff..f1a9ac9 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -26,6 +26,13 @@
 #include "config.h"	/* CONFIG_BOARDDIR */
 
 OUTPUT_ARCH(powerpc)
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+#endif
 SECTIONS
 {
 	. = CONFIG_SPL_TEXT_BASE;
@@ -53,6 +60,11 @@ SECTIONS
 	}
 	_edata  =  .;
 
+	. = .;
+	__start___ex_table = .;
+	__ex_table : { *(__ex_table) }
+	__stop___ex_table = .;
+
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
@@ -68,9 +80,21 @@ SECTIONS
 #else
 #error unknown NAND controller
 #endif
+
+#ifndef CONFIG_FSL_IFC
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+	.bootpg ADDR(.text) - 0x1000 :
+	{
+		KEEP(*(.bootpg))
+	} :text = 0xffff
+#endif
+#endif
+
+#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC
 	.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
 		KEEP(*(.resetvec))
 	} = 0xffff
+#endif
 
 	/*
 	 * Make sure that the bss segment isn't linked at 0x0, otherwise its
@@ -83,5 +107,6 @@ SECTIONS
 		*(.sbss*)
 		*(.bss*)
 	}
+	. = ALIGN(4);
 	__bss_end = .;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 0503dce..2643563 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -95,6 +95,13 @@ SECTIONS
   . = ALIGN(256);
   __init_end = .;
 
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+  .bootpg ADDR(.text) - 0x1000 :
+  {
+    KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
+  } :text = 0xffff
+  . = ADDR(.text) + 0x80000;
+#else
   .bootpg RESET_VECTOR_ADDRESS - 0xffc :
   {
     arch/powerpc/cpu/mpc85xx/start.o	(.bootpg)
@@ -117,6 +124,7 @@ SECTIONS
 #if (RESET_VECTOR_ADDRESS == 0xfffffffc)
   . |= 0x10;
 #endif
+#endif
 
   __bss_start = .;
   .bss (NOLOAD)       :
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 6f9d568..979c3c2 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -92,7 +92,7 @@ void disable_law(u8 idx)
 	return;
 }
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD_MINIMAL)
 static int get_law_entry(u8 i, struct law_entry *e)
 {
 	u32 lawar;
@@ -122,7 +122,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 	return idx;
 }
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD_MINIMAL)
 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
 	u32 idx;
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 72bb56c..7340dfe 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -45,6 +45,9 @@ COBJS-$(CONFIG_FSL_SGMII_RISER)	+= sgmii_riser.o
 ifndef CONFIG_RAMBOOT_PBL
 COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
 endif
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += spi_boot.o
+endif
 
 COBJS-$(CONFIG_MPC8541CDS)	+= cds_pci_ft.o
 COBJS-$(CONFIG_MPC8548CDS)	+= cds_pci_ft.o
@@ -52,9 +55,7 @@ COBJS-$(CONFIG_MPC8555CDS)	+= cds_pci_ft.o
 
 COBJS-$(CONFIG_MPC8536DS)	+= ics307_clk.o
 COBJS-$(CONFIG_MPC8572DS)	+= ics307_clk.o
-ifndef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_P1022DS)		+= ics307_clk.o
-endif
 COBJS-$(CONFIG_P2020DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P3041DS)		+= ics307_clk.o
 COBJS-$(CONFIG_P4080DS)		+= ics307_clk.o
diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c
index e432318..96b0680 100644
--- a/board/freescale/common/sdhc_boot.c
+++ b/board/freescale/common/sdhc_boot.c
@@ -24,6 +24,7 @@
 #include <mmc.h>
 #include <malloc.h>
 
+DECLARE_GLOBAL_DATA_PTR;
 /*
  * The environment variables are written to just after the u-boot image
  * on SDCard, so we must read the MBR to get the start address and code
@@ -31,6 +32,9 @@
  */
 #define ESDHC_BOOT_IMAGE_SIZE	0x48
 #define ESDHC_BOOT_IMAGE_ADDR	0x50
+#define ESDHC_BOOT_IMAGE_SIGN   0x55AA
+#define ESDHC_BOOT_IMAGE_SIGN_ADDR      0x1FE
+#define CONFIG_CFG_DATA_SECTOR  0
 
 int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
 {
@@ -61,3 +65,122 @@ int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
 
 	return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+void mmc_get_env(void)
+{
+	/* load environment */
+	struct mmc *mmc;
+	int err;
+	u32 offset;
+	uint blk_start, blk_cnt, ret;
+
+	mmc_initialize(gd->bd);
+	/* We register only one device. So, the dev id is always 0 */
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+	err = mmc_init(mmc);
+	if (err) {
+		puts("spl: mmc init failed!");
+		hang();
+	}
+	if (1 == mmc_get_env_addr(mmc, &offset))
+		puts("spl: mmc get env error!!\n");
+
+	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+	blk_cnt = ALIGN(CONFIG_ENV_SIZE, mmc->read_bl_len) / mmc->read_bl_len;
+
+	ret = mmc->block_dev.block_read(mmc->block_dev.dev, \
+				blk_start, blk_cnt, (uchar *)CONFIG_ENV_ADDR);
+	if (ret != blk_cnt) {
+		puts("spl: mmc read failed!");
+		hang();
+	}
+}
+
+/*
+ * The main entry for mmc booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from mmc into SDRAM and starts it from there.
+ */
+void mmc_copy_image(void)
+{
+	uint blk_start, blk_cnt, err;
+	u16 val;
+	u32 offset, code_len;
+	u32 blklen;
+	u8 *tmp_buf;
+	struct mmc *mmc;
+
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		puts("spl: mmc device not found!!\n");
+		hang();
+	}
+
+	blklen = mmc->read_bl_len;
+	tmp_buf = malloc(blklen);
+	if (!tmp_buf)
+		return;
+	memset(tmp_buf, 0, blklen);
+
+	/*
+	* Read source addr from sd card
+	*/
+	err = mmc->block_dev.block_read(0, CONFIG_CFG_DATA_SECTOR, \
+					1, (uchar *)tmp_buf);
+	if (err != 1) {
+		free(tmp_buf);
+		return;
+	}
+
+	val = *(u16 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIGN_ADDR);
+	if ((u16)ESDHC_BOOT_IMAGE_SIGN != val) {
+		free(tmp_buf);
+		return;
+	}
+
+	offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
+	offset += CONFIG_SYS_MMC_U_BOOT_OFFS;
+	/* Get the code size from offset 0x48 */
+	code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+	code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS;
+	/*
+	 * Load U-Boot image from mmc into RAM
+	*/
+	/*
+	SDHC card: code offset and length is stored in block units rather
+	* than a single byte
+	*/
+	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+	blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len;
+
+	err = mmc->block_dev.block_read(0, blk_start, blk_cnt,
+					(uchar *)CONFIG_SYS_MMC_U_BOOT_DST);
+	if (err != blk_cnt) {
+		free(tmp_buf);
+		return ;
+	}
+}
+void mmc_boot(void)
+{
+	__attribute__((noreturn)) void (*uboot)(void);
+
+	mmc_copy_image();
+	/*
+	 * Jump to U-Boot image
+	*/
+
+	/*
+	 * Clean d-cache and invalidate i-cache, to
+	 * make sure that no stale data is executed.
+	*/
+	flush_cache(CONFIG_SYS_MMC_U_BOOT_DST, CONFIG_SYS_MMC_U_BOOT_SIZE);
+	uboot = (void *)CONFIG_SYS_MMC_U_BOOT_START;
+	(*uboot)();
+}
+#endif
+
diff --git a/board/freescale/common/sdhc_boot.h b/board/freescale/common/sdhc_boot.h
new file mode 100644
index 0000000..2b5dcb9
--- /dev/null
+++ b/board/freescale/common/sdhc_boot.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SDHC_BOOT_H_
+#define __SDHC_BOOT_H_    1
+
+
+int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr);
+void mmc_get_env(void);
+void mmc_boot(void);
+
+#endif  /* __SDHC_BOOT_H_ */
+
diff --git a/board/freescale/common/spi_boot.c b/board/freescale/common/spi_boot.c
new file mode 100644
index 0000000..03f7b21
--- /dev/null
+++ b/board/freescale/common/spi_boot.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <spi_flash.h>
+
+/*
+ * The environment variables are written to just after the u-boot image
+ * on SDCard, so we must read the MBR to get the start address and code
+ * length of the u-boot image, then calculate the address of the env.
+ */
+#define ESPI_BOOT_IMAGE_SIZE   0x48
+#define ESPI_BOOT_IMAGE_ADDR   0x50
+#define CONFIG_CFG_DATA_SECTOR  0
+
+struct spi_flash *flash;
+
+void spi_get_env(void)
+{
+	int ret;
+
+	flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+				CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+	if (flash == NULL) {
+		puts("\nspi_flash_probe failed");
+		hang();
+	}
+	ret = spi_flash_read(flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, \
+			(void *)CONFIG_ENV_ADDR);
+	if (ret) {
+		puts("\nspi_flash_read failed");
+		hang();
+	}
+}
+
+/*
+ * The main entry for SPI booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from SPI into SDRAM and starts it from there.
+ */
+void spi_boot(void)
+{
+	void (*uboot)(void) __noreturn;
+	u32 offset, code_len;
+	u8 *read_buffer;
+
+	/*
+	 * Load U-Boot image from SPI flash into RAM
+	 */
+	read_buffer = malloc(flash->page_size);
+	if (!read_buffer) {
+		puts("\nmalloc failed");
+		hang();
+	}
+	memset(read_buffer, 0, flash->page_size);
+	spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR, \
+			flash->page_size, (void *)read_buffer);
+	offset = *(u32 *)(read_buffer + ESPI_BOOT_IMAGE_ADDR);
+	/* Skip spl code */
+	offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+	/* Get the code size from offset 0x48 */
+	code_len = *(u32 *)(read_buffer + ESPI_BOOT_IMAGE_SIZE);
+	/* Skip spl code */
+	code_len = code_len - CONFIG_SPL_MAX_SIZE + 8*1024;
+	spi_flash_read(flash, offset, code_len, \
+			(void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
+	/*
+	  * Jump to U-Boot image
+	  */
+	flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, \
+			CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
+	uboot = (void *) CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+	(*uboot)();
+}
+
diff --git a/board/freescale/common/spi_boot.h b/board/freescale/common/spi_boot.h
new file mode 100644
index 0000000..125dc84
--- /dev/null
+++ b/board/freescale/common/spi_boot.h
@@ -0,0 +1,26 @@
+/* Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPI_BOOT_H_
+#define __SPI_BOOT_H_    1
+
+void spi_get_env(void);
+void spi_boot(void);
+
+#endif  /* __SPI_BOOT_H_ */
+
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index 633161c..5739cf3 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -25,6 +25,9 @@ COBJS-y        += spl_minimal.o tlb.o law.o
 
 else
 
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_INIT_NORMAL) += spl.o
+endif
 COBJS-y	+= $(BOARD).o
 COBJS-y	+= ddr.o
 COBJS-y	+= law.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
new file mode 100644
index 0000000..32acddc
--- /dev/null
+++ b/board/freescale/p1022ds/spl.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <malloc.h>
+#ifdef CONFIG_SDCARD
+#include <mmc.h>
+#include <i2c.h>
+#include "../common/sdhc_boot.h"
+#endif
+#ifdef CONFIG_SPIFLASH
+#include <i2c.h>
+#include "../common/ngpixis.h"
+#include "../common/spi_boot.h"
+#endif
+
+static const u32 sysclk_tbl[] = {
+	66666000, 7499900, 83332500, 8999900,
+	99999000, 11111000, 12499800, 13333200
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void hang(void)
+{
+	puts("### ERROR ### Please RESET the board ###\n");
+	for (;;)
+		;
+}
+
+ulong get_effective_memsize(void)
+{
+	return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+	int px_spd;
+	u32 plat_ratio, sys_clk, bus_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	console_init_f();
+
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	/* Set pmuxcr to allow both i2c1 and i2c2 */
+	setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
+	setbits_be32(&gur->pmuxcr,
+		in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+#ifdef CONFIG_SPIFLASH
+	/* Enable the SPI */
+	clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+#endif
+	/* Read back the register to synchronize the write. */
+	in_be32(&gur->pmuxcr);
+#endif
+
+	/* initialize selected port with appropriate baud rate */
+	px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+	sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	bus_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+			bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SDCARD
+	puts("\nSD boot...\n");
+#endif
+#ifdef CONFIG_NAND
+	puts("\nNAND boot...\n");
+#endif
+#ifdef CONFIG_SPIFLASH
+	puts("\nSPI Flash boot...\n");
+#endif
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SPL_RELOC_STACK, 0,
+			CONFIG_SPL_RELOC_TEXT_BASE);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)CONFIG_SPL_GD_ADDR;
+	bd_t *bd;
+
+	memset(gd, 0, sizeof(gd_t));
+	bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L2_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, \
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+#ifdef CONFIG_SDCARD
+	/* load environment */
+	mmc_get_env();
+#elif defined(CONFIG_SPIFLASH)
+	spi_get_env();
+#endif
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+	gd->ram_size = initdram(0);
+	puts("Second program loader running in sram...\n");
+
+#ifdef CONFIG_SDCARD
+	mmc_boot();
+#elif defined(CONFIG_SPIFLASH)
+	spi_boot();
+#endif
+#endif	/* defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) */
+#ifdef CONFIG_NAND
+	nand_boot();
+#endif
+}
diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index ebf5dd7..402d877 100644
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -74,7 +74,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_4K, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
+#if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
+	!defined(CONFIG_SPL_COMMON_INIT_DDR)
 	/* **** - eSDHC/eSPI/NAND boot */
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 			MAS3_SX|MAS3_SW|MAS3_SR, 0,
@@ -94,6 +95,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 			0, 10, BOOKE_PAGESZ_16K, 1),
 #endif
 
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+			0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/common/Makefile b/common/Makefile
index 0e0fff1..bc80414 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -225,6 +225,11 @@ COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_flags.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
+COBJS-$(CONFIG_SPL_HWCONFIG_SUPPORT) += hwconfig.o
+COBJS-$(CONFIG_SPL_INIT_DDR_SUPPORT) += ddr_spd.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
 endif
 COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
 COBJS-y += console.o
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
new file mode 100644
index 0000000..79f91fc
--- /dev/null
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -0,0 +1,82 @@
+----------------------------------------
+Booting from On-Chip ROM (eSDHC or eSPI)
+----------------------------------------
+
+boot_format is a tool to write SD bootable images to a filesystem and build
+SD/SPI images to a binary file for writing later.
+
+When booting from an SD card/MMC, boot_format puts the configuration file and
+the RAM-based U-Boot image on the card.
+When booting from an EEPROM, boot_format generates a binary image that is used
+to boot from this EEPROM.
+
+Where to get boot_format:
+========================
+
+you can browse it online at:
+http://git.freescale.com/git/cgit.cgi/ppc/sdk/boot-format.git/
+
+Building
+========
+
+Run the following to build this project
+
+	$ make
+
+Execution
+=========
+
+boot_format runs under a regular Linux machine and requires a super user mode
+to run. Execute boot_format as follows.
+
+For building SD images by writing directly to a file system on SD media:
+
+	$ boot_format $config u-boot.bin -sd $device
+
+Where $config is the included config.dat file for your platform and $device
+is the target block device for the SD media on your computer.
+
+For build binary images directly a local file:
+
+	$ boot_format $config u-boot.bin -spi $file
+
+Where $file is the target file. Also keep in mind the u-boot.bin file needs
+to be the u-boot built for your particular platform and target media.
+
+Hint: To generate a u-boot.bin for a P1022DS booting from SD I would run the
+following in the u-boot repository:
+
+	$ make P1022DS_SDCARD
+
+Configuration Files
+===================
+
+Below are the configuration files to be used with a particular platform. Keep
+in mind that some of these config files are tied to the platforms DDR speed.
+Please see the SoC reference manual for more documentation.
+
+P1022DS		config_sram_p1022ds.dat
+P2020DS		config_sram_p2020ds.dat
+P2010DS		config_sram_p2020ds.dat
+P1020RDB	config_ddr2_1g_p1020rdb_533M.dat
+P1020RDB	config_ddr2_1g_p1020rdb_667M.dat
+P2020RDB	config_ddr2_1g_p2020rdb_800M.dat
+P2020RDB	config_ddr2_1g_p2020rdb_667M.dat
+P2020RDB	config_ddr3_1gb_64bit_p2020rdb_pc.dat
+P2010RDB	config_ddr3_1gb_64bit_p2020rdb_pc.dat
+P1020RDB	config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1011RDB	config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1010RDB	config_ddr3_1gb_p1010rdb_800M.dat
+P1014RDB	config_ddr3_1gb_p1014rdb_800M.dat
+P1021RDB	config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1012RDB	config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1022DS		config_ddr3_2gb_p1022ds.dat
+P1013DS		config_ddr3_2gb_p1022ds.dat
+P1024RDB	config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1013RDB	config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1025RDB	config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1016RDB	config_ddr3_1gb_p1_p2_rdb_pc_667M.dat
+P1020UTM	config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+P1020MBG	config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
+MPC8536DS	config_ddr2_512m_mpc8536ds_667M.dat
+
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 15eafd4..dedd060 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -19,19 +19,72 @@
 #endif
 
 #ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_NORMAL
+#define CONFIG_SPL_INIT_DDR_SUPPORT
+#define CONFIG_SPL_HWCONFIG_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SPL_ADDR_MAP_SUPPORT
+#endif
+#define CONFIG_SPL_UTILITYLIB_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                  /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE            0x11001000
+#define CONFIG_SPL_TEXT_BASE            0xf8f81000
+#define CONFIG_SPL_PAD_TO               0x18000
+#define CONFIG_SPL_MAX_SIZE             (96 * 1024)
+#define CONFIG_SYS_MMC_U_BOOT_SIZE      (512 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST       (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_START     (0x11000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS      (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT         "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_TEXT_BASE		0x11000000
-#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_NORMAL
+#define CONFIG_SPL_INIT_DDR_SUPPORT
+#define CONFIG_SPL_HWCONFIG_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SPL_ADDR_MAP_SUPPORT
+#endif
+#define CONFIG_SPL_UTILITYLIB_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_FSL_LAW                  /* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE            0x11001000
+#define CONFIG_SPL_TEXT_BASE            0xf8f81000
+#define CONFIG_SPL_PAD_TO               0x18000
+#define CONFIG_SPL_MAX_SIZE             (96 * 1024)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE      (512 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST       (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START     (0x11000000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS      (96 << 10)
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#define CONFIG_SYS_LDSCRIPT         "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_COMMON_INIT_DDR
+#endif
 #endif
 
 #define CONFIG_NAND_FSL_ELBC
@@ -44,7 +97,6 @@
 #define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-
 #define CONFIG_SYS_TEXT_BASE           0x00201000
 #define CONFIG_SPL_TEXT_BASE           0xfffff000
 #define CONFIG_SPL_MAX_SIZE            0x1000
@@ -55,6 +107,9 @@
 #define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0
 #define CONFIG_SYS_LDSCRIPT            "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_BUILD_MINIMAL
+#endif
 #endif
 
 /* High Level Configuration Options */
@@ -81,7 +136,6 @@
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
-
 #define CONFIG_ENABLE_36BIT_PHYS
 
 #ifdef CONFIG_PHYS_64BIT
@@ -152,9 +206,9 @@
 #define CONFIG_SYS_DDR_CLK_CTRL		0x02800000
 #define CONFIG_SYS_DDR_CONTROL		0xc7000008
 #define CONFIG_SYS_DDR_CONTROL_2	0x24401041
-#define	CONFIG_SYS_DDR_TIMING_4		0x00220001
-#define	CONFIG_SYS_DDR_TIMING_5		0x02401400
-#define	CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x02401400
+#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
 #define CONFIG_SYS_DDR_WRLVL_CONTROL	0x8675f608
 
 /*
@@ -282,9 +336,10 @@
 #define PIXIS_ELBC_SPI_MASK	0xc0
 #define PIXIS_SPI		0x80
 
+
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
 
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
@@ -294,6 +349,26 @@
 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+
+#define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE              (256 << 10)
+#define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0xf8f81000
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(32 << 10)
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(96 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
+#endif
+#endif
+
+
+/*
  * Serial Port
  */
 #define CONFIG_CONS_INDEX		1
@@ -301,7 +376,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND)
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
 
@@ -524,8 +599,9 @@
 /*
  * Environment
  */
-#ifdef CONFIG_RAMBOOT_SPIFLASH
+#ifdef CONFIG_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (96 << 10))
 #define CONFIG_ENV_SPI_BUS	0
 #define CONFIG_ENV_SPI_CS	0
 #define CONFIG_ENV_SPI_MAX_HZ	10000000
@@ -533,8 +609,10 @@
 #define CONFIG_ENV_SIZE		0x2000	/* 8KB */
 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
 #define CONFIG_ENV_SECT_SIZE	0x10000
-#elif defined(CONFIG_RAMBOOT_SDCARD)
+#elif defined(CONFIG_SDCARD)
 #define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_FSL_FIXED_MMC_LOCATION
+#define CONFIG_ENV_ADDR         (CONFIG_SYS_INIT_L2_ADDR + (96 << 10))
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #elif defined(CONFIG_NAND)
diff --git a/lib/Makefile b/lib/Makefile
index e901cc7..ab12e63 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -66,6 +66,11 @@ endif
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
+COBJS-$(CONFIG_SPL_ADDR_MAP_SUPPORT) += addr_map.o
+COBJS-$(CONFIG_SPL_UTILITYLIB_SUPPORT) += hashtable.o
+COBJS-$(CONFIG_SPL_UTILITYLIB_SUPPORT) += display_options.o
+COBJS-$(CONFIG_SPL_UTILITYLIB_SUPPORT) += errno.o
+
 endif
 COBJS-$(CONFIG_BCH) += bch.o
 COBJS-y += crc32.o
diff --git a/spl/Makefile b/spl/Makefile
index b5a8de7..3a3b868 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -51,6 +51,9 @@ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
 endif
 ifeq ($(CPU),mpc85xx)
 LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+ifdef CONFIG_SPL_INIT_DDR_SUPPORT
+LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+endif
 endif
 ifeq ($(CPU),mpc86xx)
 LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
