From patchwork Thu May 2 14:04:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 241018 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id ADCE92C00A3 for ; Fri, 3 May 2013 00:28:47 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 32EC94A209; Thu, 2 May 2013 16:28:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id C8cu4W1V-Gy5; Thu, 2 May 2013 16:28:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6ECBF4A217; Thu, 2 May 2013 16:28:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DB5B34A141 for ; Thu, 2 May 2013 16:23:57 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 9imp1wHo9nQK for ; Thu, 2 May 2013 16:23:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe002.messaging.microsoft.com [207.46.163.25]) by theia.denx.de (Postfix) with ESMTPS id 6CEC54A2BC for ; Thu, 2 May 2013 16:20:32 +0200 (CEST) Received: from mail95-co9-R.bigfish.com (10.236.132.240) by CO9EHSOBE036.bigfish.com (10.236.130.99) with Microsoft SMTP Server id 14.1.225.23; Thu, 2 May 2013 14:04:45 +0000 Received: from mail95-co9 (localhost [127.0.0.1]) by mail95-co9-R.bigfish.com (Postfix) with ESMTP id 6A7D58C0190; Thu, 2 May 2013 14:04:45 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1f42h1fc6h1ee6h1de0h1fdah1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1155h) Received: from mail95-co9 (localhost.localdomain [127.0.0.1]) by mail95-co9 (MessageSwitch) id 1367503484636565_29440; Thu, 2 May 2013 14:04:44 +0000 (UTC) Received: from CO9EHSMHS029.bigfish.com (unknown [10.236.132.235]) by mail95-co9.bigfish.com (Postfix) with ESMTP id 8EECCCA0091; Thu, 2 May 2013 14:04:44 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS029.bigfish.com (10.236.130.39) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 2 May 2013 14:04:44 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.328.11; Thu, 2 May 2013 14:04:43 +0000 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.244.56]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r42E4OiO026112; Thu, 2 May 2013 07:04:41 -0700 From: Fabio Estevam To: Date: Thu, 2 May 2013 11:04:15 -0300 Message-ID: <1367503462-24742-2-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1367503462-24742-1-git-send-email-fabio.estevam@freescale.com> References: <1367503462-24742-1-git-send-email-fabio.estevam@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: marex@denx.de, u-boot@lists.denx.de, Fabio@theia.denx.de, Estevam , otavio@ossystems.com.br Subject: [U-Boot] [PATCH v2 1/8] mx23: Fix pad voltage selection bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On mx23 the pad voltage selection bit needs to be always '0', since '1' is a reserved value. For example: Pin 108, EMI_A06 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Fix the pad voltage definitions for the mx23 case. Signed-off-by: Fabio Estevam --- Changes since v1: - Newly introduced arch/arm/include/asm/arch-mxs/iomux.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h index 4288715..66dcd36 100644 --- a/arch/arm/include/asm/arch-mxs/iomux.h +++ b/arch/arm/include/asm/arch-mxs/iomux.h @@ -70,8 +70,13 @@ typedef u32 iomux_cfg_t; #define PAD_12MA 2 #define PAD_16MA 3 +#if defined CONFIG_MX28 #define PAD_1V8 0 #define PAD_3V3 1 +#else +#define PAD_1V8 0 +#define PAD_3V3 0 +#endif #define PAD_NOPULL 0 #define PAD_PULLUP 1