From patchwork Mon Mar 25 17:33:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 230807 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AEC8D2C009B for ; Tue, 26 Mar 2013 04:38:46 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5A3624A163; Mon, 25 Mar 2013 18:37:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bSsjckhj1HqP; Mon, 25 Mar 2013 18:37:39 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F2D2A4A1D5; Mon, 25 Mar 2013 18:36:18 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5721C4A1EB for ; Mon, 25 Mar 2013 18:35:58 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vhNiza80jm6U for ; Mon, 25 Mar 2013 18:35:56 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe001.messaging.microsoft.com [216.32.180.184]) by theia.denx.de (Postfix) with ESMTPS id 695D34A111 for ; Mon, 25 Mar 2013 18:34:41 +0100 (CET) Received: from mail192-co1-R.bigfish.com (10.243.78.228) by CO1EHSOBE011.bigfish.com (10.243.66.74) with Microsoft SMTP Server id 14.1.225.23; Mon, 25 Mar 2013 17:34:37 +0000 Received: from mail192-co1 (localhost [127.0.0.1]) by mail192-co1-R.bigfish.com (Postfix) with ESMTP id 38319C60846 for ; Mon, 25 Mar 2013 17:34:37 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1f42h1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1155h) Received: from mail192-co1 (localhost.localdomain [127.0.0.1]) by mail192-co1 (MessageSwitch) id 1364232874631533_18904; Mon, 25 Mar 2013 17:34:34 +0000 (UTC) Received: from CO1EHSMHS010.bigfish.com (unknown [10.243.78.226]) by mail192-co1.bigfish.com (Postfix) with ESMTP id 98464A401B0 for ; Mon, 25 Mar 2013 17:34:34 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS010.bigfish.com (10.243.66.20) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 25 Mar 2013 17:34:34 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.328.11; Mon, 25 Mar 2013 17:33:48 +0000 Received: from oslab-l1.am.freescale.net ([10.214.80.134]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r2PHXhsm018974; Mon, 25 Mar 2013 10:33:47 -0700 From: York Sun To: Date: Mon, 25 Mar 2013 10:33:11 -0700 Message-ID: <1364232811-30856-3-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1364232811-30856-1-git-send-email-yorksun@freescale.com> References: <1364232811-30856-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: u-boot@lists.denx.de, Minghuan@theia.denx.de Subject: [U-Boot] [Patch v2, batch 2 03/23] powerpc/pcie: add PCIe version 3.x support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Roy ZANG T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. Signed-off-by: Roy Zang Signed-off-by: Minghuan Lian --- arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/fsl_pci.h | 35 +++++++++++++++++++++++++++-- drivers/pci/fsl_pci_init.c | 20 ++++++++++++----- include/pci.h | 7 ------ 4 files changed, 48 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 352e303..3740785 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -543,6 +543,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_PCI_VER_3_X #elif defined(CONFIG_PPC_B4420) #define CONFIG_SYS_PPC64 /* 64-bit core */ diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h index 49bd2bf..0c41361 100644 --- a/arch/powerpc/include/asm/fsl_pci.h +++ b/arch/powerpc/include/asm/fsl_pci.h @@ -1,5 +1,5 @@ /* - * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. + * Copyright 2007,2009-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -27,6 +27,34 @@ #define PEX_IP_BLK_REV_2_2 0x02080202 #define PEX_IP_BLK_REV_2_3 0x02080203 +#define PEX_IP_BLK_REV_3_0 0x02080300 + +/* Freescale-specific PCI config registers */ +#define FSL_PCI_PBFR 0x44 + +#ifdef CONFIG_SYS_FSL_PCI_VER_3_X +/* Currently only the PCIe capability is used, so hardcode the offset. + * if more capabilities need to be justified, the capability link method + * should be applied here + */ +#define FSL_PCIE_CAP_ID 0x70 +#define PCI_DCR 0x78 /* PCIe Device Control Register */ +#define PCI_DSR 0x7a /* PCIe Device Status Register */ +#define PCI_LSR 0x82 /* PCIe Link Status Register */ +#define PCI_LCR 0x80 /* PCIe Link Control Register */ +#else +#define FSL_PCIE_CAP_ID 0x4c +#define PCI_DCR 0x54 /* PCIe Device Control Register */ +#define PCI_DSR 0x56 /* PCIe Device Status Register */ +#define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LCR 0x5c /* PCIe Link Control Register */ +#endif + +#define FSL_PCIE_CFG_RDY 0x4b0 +#define FSL_PROG_IF_AGENT 0x1 + +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); @@ -163,7 +191,10 @@ typedef struct ccsr_pci { u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ char res23[200]; u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ - char res24[252]; + char res24[16]; + u32 pex_csr0; /* 0xf14 - PEX Control/Status register 0*/ + u32 pex_csr1; /* 0xf18 - PEX Control/Status register 1*/ + char res25[228]; } ccsr_fsl_pci_t; #define PCIE_CONFIG_PC 0x00020000 #define PCIE_CONFIG_OB_CK 0x00002000 diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 77ac1f7..d881375 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -41,12 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; #include #include -/* Freescale-specific PCI config registers */ -#define FSL_PCI_PBFR 0x44 -#define FSL_PCIE_CAP_ID 0x4c -#define FSL_PCIE_CFG_RDY 0x4b0 -#define FSL_PROG_IF_AGENT 0x1 - #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS 0 #endif @@ -437,6 +431,15 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) udelay(1); #endif if (pcie_cap == PCI_CAP_ID_EXP) { + if (block_rev >= PEX_IP_BLK_REV_3_0) { +#define PEX_CSR0_LTSSM_MASK 0xFC +#define PEX_CSR0_LTSSM_SHIFT 2 + ltssm = (in_be32(&pci->pex_csr0) + & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT; + enabled = (ltssm == 0x11) ? 1 : 0; + } else { + /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */ + /* enabled = ltssm >= PCI_LTSSM_L0; */ pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); enabled = ltssm >= PCI_LTSSM_L0; @@ -469,6 +472,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) PCI_BASE_ADDRESS_0, pcicsrbar); } #endif + } #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { @@ -577,6 +581,10 @@ int fsl_is_pci_agent(struct pci_controller *hose) u8 prog_if; pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if); + /* Programming Interface (PCI_CLASS_PROG) + * 0 == pci host or pcie root-complex, + * 1 == pci agent or pcie end-point + */ return (prog_if == FSL_PROG_IF_AGENT); } } diff --git a/include/pci.h b/include/pci.h index 15f583f..c0ed553 100644 --- a/include/pci.h +++ b/include/pci.h @@ -426,13 +426,6 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 -#define PCI_DCR 0x54 /* PCIe Device Control Register */ -#define PCI_DSR 0x56 /* PCIe Device Status Register */ -#define PCI_LSR 0x5e /* PCIe Link Status Register */ -#define PCI_LCR 0x5c /* PCIe Link Control Register */ -#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ -#define PCI_LTSSM_L0 0x16 /* L0 state */ - /* Include the ID list */ #include