Message ID | 1363973052-25918-3-git-send-email-yorksun@freescale.com |
---|---|
State | Superseded |
Headers | show |
Dear York Sun, In message <1363973052-25918-3-git-send-email-yorksun@freescale.com> you wrote: > From: Tang Yuantian <Yuantian.Tang@freescale.com> > > For T4/B4, the clockgen node compatible string is updated to version 2. > Add clock-frequency setting for this new version. > > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> > --- > arch/powerpc/cpu/mpc85xx/fdt.c | 2 ++ > 1 file changed, 2 insertions(+) CHECK: Alignment should match open parenthesis #125: FILE: arch/powerpc/cpu/mpc85xx/fdt.c:667: + do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); Best regards, Wolfgang Denk
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 24eb978..cda6ad6 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -663,6 +663,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_FSL_CORENET do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0", "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); + do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2", + "clock-frequency", CONFIG_SYS_CLK_FREQ, 1); #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);