From patchwork Fri Feb 8 09:14:46 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo Serra X-Patchwork-Id: 219069 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3FF572C0080 for ; Fri, 8 Feb 2013 20:15:25 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BBA924A0C7; Fri, 8 Feb 2013 10:15:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OGU+fi-u11CT; Fri, 8 Feb 2013 10:15:22 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B72144A0B5; Fri, 8 Feb 2013 10:15:21 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8B5EE4A0A1 for ; Fri, 8 Feb 2013 10:15:17 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vDFJ-6WQXOrL for ; Fri, 8 Feb 2013 10:15:17 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f174.google.com (mail-wi0-f174.google.com [209.85.212.174]) by theia.denx.de (Postfix) with ESMTPS id 00EBA4A0BB for ; Fri, 8 Feb 2013 10:15:10 +0100 (CET) Received: by mail-wi0-f174.google.com with SMTP id hi8so543500wib.13 for ; Fri, 08 Feb 2013 01:15:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=YQmK1Io/5AVuTPVTTokOyatBJ33Odpr+0SAlLyaJDhc=; b=gIxV5+HcFnnwL0hfTUd43CROap16DhbVkU/ScztriptR3D0o/ZLi10sQ5/FosDq7Mg 5yo4LdP6mHj87rYRpQa9BSyifXOyg0arlF9QtEQmOjtHICDxiEnUMtRGhBUyMiRyrUCU 0BUTilZyOFE4sgkz0JAzt3W0TlssyrN5WZuXhTbpqJaBy06BirS9KRjZ2BcmboCA6phN yZKlHqmW9KF2OAvffDUICL1GMxO9KGmYvK/V/lVx9VbMpYrHKfUkth4Ia+rA83U5hAKQ zMWhZU0FUzAenWJqkezJQu5umrWX3jZuqkJCgOTG1wuPR+0xWgig8Blf6GDIft0N6d9A obzg== X-Received: by 10.180.8.197 with SMTP id t5mr976813wia.27.1360314909603; Fri, 08 Feb 2013 01:15:09 -0800 (PST) Received: from localhost.localdomain (43.Red-2-139-180.staticIP.rima-tde.net. [2.139.180.43]) by mx.google.com with ESMTPS id fx5sm14176704wib.11.2013.02.08.01.15.08 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 08 Feb 2013 01:15:09 -0800 (PST) From: Enric Balletbo i Serra To: u-boot@lists.denx.de, trini@ti.com, javier@dowhile0.org, elezegarcia@gmail.com Date: Fri, 8 Feb 2013 10:14:46 +0100 Message-Id: <1360314889-16955-2-git-send-email-eballetbo@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1360314889-16955-1-git-send-email-eballetbo@gmail.com> References: <1360314889-16955-1-git-send-email-eballetbo@gmail.com> Cc: Enric Balletbo i Serra Subject: [U-Boot] [PATCHv2 1/4] SPL: ONENAND: Fix some ONENAND related defines. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Enric Balletbo i Serra Some ONENAND related defines use the term ONE_NAND instead of ONENAND, as the technology name is ONENAND this patch replaces all these defines. Signed-off-by: Enric Balletbo i Serra --- arch/arm/cpu/arm1136/mx35/generic.c | 2 +- arch/arm/include/asm/arch-mx35/spl.h | 2 +- arch/arm/include/asm/arch-omap3/spl.h | 2 +- arch/arm/include/asm/arch-omap4/spl.h | 2 +- arch/arm/include/asm/arch-omap5/spl.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c index d11e6f6..46f4b64 100644 --- a/arch/arm/cpu/arm1136/mx35/generic.c +++ b/arch/arm/cpu/arm1136/mx35/generic.c @@ -519,7 +519,7 @@ u32 spl_boot_device(void) case RCSR_MEM_TYPE_NOR: return BOOT_DEVICE_NOR; case RCSR_MEM_TYPE_ONENAND: - return BOOT_DEVICE_ONE_NAND; + return BOOT_DEVICE_ONENAND; default: return BOOT_DEVICE_NONE; } diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h index 91d11ae..3ca4c94 100644 --- a/arch/arm/include/asm/arch-mx35/spl.h +++ b/arch/arm/include/asm/arch-mx35/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index 404e16a..dec4dac 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -26,7 +26,7 @@ #define BOOT_DEVICE_NONE 0 #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_NAND 2 -#define BOOT_DEVICE_ONE_NAND 3 +#define BOOT_DEVICE_ONENAND 3 #define BOOT_DEVICE_MMC2 5 /*emmc*/ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_XIPWAIT 7 diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index cec84dc..4e094f9 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 0xFF diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index d125c61..323cd63 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -27,7 +27,7 @@ #define BOOT_DEVICE_XIP 1 #define BOOT_DEVICE_XIPWAIT 2 #define BOOT_DEVICE_NAND 3 -#define BOOT_DEVICE_ONE_NAND 4 +#define BOOT_DEVICE_ONENAND 4 #define BOOT_DEVICE_MMC1 5 #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7