From patchwork Wed Oct 31 05:24:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 195738 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 38B062C007E for ; Wed, 31 Oct 2012 16:24:51 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B7C5A4A395; Wed, 31 Oct 2012 06:24:47 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id q0eRuNFE3RQd; Wed, 31 Oct 2012 06:24:47 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 400944A398; Wed, 31 Oct 2012 06:24:46 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 780C14A398 for ; Wed, 31 Oct 2012 06:24:45 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MRI8jPVB3y+h for ; Wed, 31 Oct 2012 06:24:44 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-da0-f44.google.com (mail-da0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 706164A395 for ; Wed, 31 Oct 2012 06:24:42 +0100 (CET) Received: by mail-da0-f44.google.com with SMTP id h15so465627dan.3 for ; Tue, 30 Oct 2012 22:24:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer; bh=x6bapttVQ0FPM2+7zi+4InhhnXcNQzOR0FTmCa/QYFk=; b=FD80EXnhM79kmELrxgAjTpv7u6G9cu2mSjHrDbHCz2KwYMkWFgWTE+eyBqMTxBL9cD bYT9/qtMlcNxL+eMqIXicX+WObvDTNkTb4x8Tui1YY5wyiJAW7I+puh5knnIwV0BLpIt CW7M/Y8Zhp5v7U605Wal0Sq07dOKEopbn37vIvbtMjrQzgP56OZ+hnjyhK8aRDZxWfDj IH4LOu52HB4iOSVZWCpMztIJuX6tNn5q4ym3nLnMP4Ey+CreHhSVCXLVW2YK+6z4ICSX MMxayCtS97YvZMi6CP2+GQJu3lbiY/w01JtkSb5Q724L5FjC43wmt2JhZYb5rQW4DvfH 8aag== Received: by 10.68.209.136 with SMTP id mm8mr108679503pbc.146.1351661080642; Tue, 30 Oct 2012 22:24:40 -0700 (PDT) Received: from localhost.localdomain (ip68-230-53-52.ph.ph.cox.net. [68.230.53.52]) by mx.google.com with ESMTPS id iq3sm1721736pbc.5.2012.10.30.22.24.38 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 30 Oct 2012 22:24:39 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Tue, 30 Oct 2012 22:24:37 -0700 Message-Id: <1351661077-17936-1-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 Subject: [U-Boot] [PATCH] omap3: Rework board.c for !CONFIG_SYS_L2CACHE_OFF X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de When CONFIG_SYS_L2CACHE_OFF is defined we end up with a few warnings currently. Re-order functions so that we don't have that anymore. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap3/board.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 9cee1d9..f3cd81a 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR; /* Declarations */ extern omap3_sysinfo sysinfo; static void omap3_setup_aux_cr(void); +#ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); +#endif static const struct gpio_bank gpio_bank_34xx[6] = { { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX }, @@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } } -static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) -{ - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - - /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); -} - static void omap3_setup_aux_cr(void) { /* Workaround for Cortex-A8 errata: #454179 #430973 @@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void) } #ifndef CONFIG_SYS_L2CACHE_OFF +static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + /* Write ACR - affects non-secure banked bits */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); +} + /* Invalidate the entire L2 cache from secure mode */ static void omap3_invalidate_l2_cache_secure(void) {