From patchwork Sat Oct 6 14:16:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Ying X-Patchwork-Id: 189755 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 845082C0328 for ; Sun, 7 Oct 2012 06:07:48 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D88F528086; Sat, 6 Oct 2012 21:07:44 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QM7nC8QkO4GD; Sat, 6 Oct 2012 21:07:44 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7235728087; Sat, 6 Oct 2012 21:07:42 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6F7F228085 for ; Sat, 6 Oct 2012 17:00:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id k1GwasaXtySX for ; Sat, 6 Oct 2012 17:00:53 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from tx2outboundpool.messaging.microsoft.com (tx2ehsobe002.messaging.microsoft.com [65.55.88.12]) by theia.denx.de (Postfix) with ESMTPS id C96DB28081 for ; Sat, 6 Oct 2012 17:00:51 +0200 (CEST) Received: from mail55-tx2-R.bigfish.com (10.9.14.254) by TX2EHSOBE012.bigfish.com (10.9.40.32) with Microsoft SMTP Server id 14.1.225.23; Sat, 6 Oct 2012 15:00:49 +0000 Received: from mail55-tx2 (localhost [127.0.0.1]) by mail55-tx2-R.bigfish.com (Postfix) with ESMTP id 6553642016F for ; Sat, 6 Oct 2012 15:00:49 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839he5bhf0ah11b5h121eh1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1155h) Received: from mail55-tx2 (localhost.localdomain [127.0.0.1]) by mail55-tx2 (MessageSwitch) id 1349535647284457_8748; Sat, 6 Oct 2012 15:00:47 +0000 (UTC) Received: from TX2EHSMHS041.bigfish.com (unknown [10.9.14.240]) by mail55-tx2.bigfish.com (Postfix) with ESMTP id 428132C0049 for ; Sat, 6 Oct 2012 15:00:47 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS041.bigfish.com (10.9.99.141) with Microsoft SMTP Server (TLS) id 14.1.225.23; Sat, 6 Oct 2012 15:00:46 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.309.3; Sat, 6 Oct 2012 10:00:46 -0500 Received: from shlinux1.ap.freescale.net ([10.213.130.145]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id q96F0g3D028045 for ; Sat, 6 Oct 2012 08:00:45 -0700 Received: by shlinux1.ap.freescale.net (Postfix, from userid 1011) id F30451AE0C2; Sat, 6 Oct 2012 22:16:09 +0800 (CST) From: Liu Ying To: Date: Sat, 6 Oct 2012 22:16:04 +0800 Message-ID: <1349532964-8480-1-git-send-email-Ying.liu@freescale.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.net X-Mailman-Approved-At: Sat, 06 Oct 2012 21:07:40 +0200 Cc: fabio.estevam@freescale.com, liu.y.victor@gmail.com, Liu Ying , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/1] ipu common: reset ipuv3 correctly X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Liu Ying This patch checks self-clear sw_ipu_rst bit in SCR register of SRC controller to be cleared after setting it to high to reset IPUv3. This makes sure that IPUv3 finishes sofware reset. A timeout mechanism is added to stop polling on the bit status in case the bit could not be cleared by the hardware automatically within 10 millisecond. Signed-off-by: Liu Ying --- drivers/video/ipu_common.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c index 2020da9..fcc1745 100644 --- a/drivers/video/ipu_common.c +++ b/drivers/video/ipu_common.c @@ -94,6 +94,7 @@ struct ipu_ch_param { temp1; \ }) +#define IPU_SW_RST_TOUT_USEC (10000) void clk_enable(struct clk *clk) { @@ -392,11 +393,20 @@ void ipu_reset(void) { u32 *reg; u32 value; + int timeout = IPU_SW_RST_TOUT_USEC; reg = (u32 *)SRC_BASE_ADDR; value = __raw_readl(reg); value = value | SW_IPU_RST; __raw_writel(value, reg); + + while (__raw_readl(reg) & SW_IPU_RST) { + udelay(1); + if (!(timeout--)) { + printf("ipu software reset timeout\n"); + break; + } + }; } /*