From patchwork Tue Oct 2 13:16:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 188513 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 63B222C0094 for ; Tue, 2 Oct 2012 23:17:44 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5F67128101; Tue, 2 Oct 2012 15:17:33 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VJOUfzIsx3B1; Tue, 2 Oct 2012 15:17:33 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C023528103; Tue, 2 Oct 2012 15:17:26 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7460C280FA for ; Tue, 2 Oct 2012 15:17:25 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3gpAQ2UTQwth for ; Tue, 2 Oct 2012 15:17:25 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f44.google.com (mail-pb0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTPS id 17B6B280ED for ; Tue, 2 Oct 2012 15:17:11 +0200 (CEST) Received: by mail-pb0-f44.google.com with SMTP id ro8so8995393pbb.3 for ; Tue, 02 Oct 2012 06:17:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=2qG0gnqf1KmhKpKc1zu04fFszncEi2sj82U4pCkpEFA=; b=Fv9oUjtb0kKFq7bNlM7kHRVjnyX9LGS4pS+nt2pXQsOfQ1AwXBMv9fmeRZEkCkIkUj D4hl155QDVZjOZFb5QdE+4K+LnrkxKkx4H2vmjfDGUGwhunU2U0eA37d80KN0KA3Wwgl mNJ+TE/Eb05p4ZIKNxEFJuTp9kKY+5HGUBXNvz3U7eThHO8AWR5cyF7i+6jMttqnkMqq Y0p8Ed8S0Tqznkcgo5YAGATMBogYoedsDqFgCzP2Z5oBsmRVIQ8WopwXNtBfPRk9pgZU 65ao65IoJ7yF5DbITqnEEHis0km8A+ZTmjKq3rA72PcnyPypqg6eMspWHKNv+PC2ms3J 9j1g== Received: by 10.66.73.230 with SMTP id o6mr44129655pav.45.1349183830824; Tue, 02 Oct 2012 06:17:10 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id d1sm714150pay.25.2012.10.02.06.17.08 (version=SSLv3 cipher=OTHER); Tue, 02 Oct 2012 06:17:10 -0700 (PDT) From: Chander Kashyap To: u-boot@lists.denx.de Date: Tue, 2 Oct 2012 18:46:49 +0530 Message-Id: <1349183809-15976-4-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349183809-15976-1-git-send-email-chander.kashyap@linaro.org> References: <1349183809-15976-1-git-send-email-chander.kashyap@linaro.org> X-Gm-Message-State: ALoCoQkK/0vAlqnbZxMC0PPKQ2uP24K8iOVOVXAdznM/bUPsPMHpMmtx3nRRvYKrYMMeWOO5kNQn Cc: linaro-dev@lists.linaro.org, patches@linaro.org Subject: [U-Boot] [PATCH v2 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap --- arch/arm/include/asm/arch-exynos/gpio.h | 85 +++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 4db8fd6..cfe1024 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -79,6 +79,67 @@ struct exynos4_gpio_part3 { struct s5p_gpio_bank z; }; +struct exynos4x12_gpio_part1 { + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank res1[0x5]; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank res2[0x2]; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; +}; + +struct exynos4x12_gpio_part2 { + struct s5p_gpio_bank res1[0x2]; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank y0; + struct s5p_gpio_bank y1; + struct s5p_gpio_bank y2; + struct s5p_gpio_bank y3; + struct s5p_gpio_bank y4; + struct s5p_gpio_bank y5; + struct s5p_gpio_bank y6; + struct s5p_gpio_bank res2[0x3]; + struct s5p_gpio_bank m0; + struct s5p_gpio_bank m1; + struct s5p_gpio_bank m2; + struct s5p_gpio_bank m3; + struct s5p_gpio_bank m4; + struct s5p_gpio_bank res3[0x48]; + struct s5p_gpio_bank x0; + struct s5p_gpio_bank x1; + struct s5p_gpio_bank x2; + struct s5p_gpio_bank x3; +}; + +struct exynos4x12_gpio_part3 { + struct s5p_gpio_bank z; +}; + +struct exynos4x12_gpio_part4 { + struct s5p_gpio_bank v0; + struct s5p_gpio_bank v1; + struct s5p_gpio_bank res1[0x1]; + struct s5p_gpio_bank v2; + struct s5p_gpio_bank v3; + struct s5p_gpio_bank res2[0x1]; + struct s5p_gpio_bank v4; +}; + struct exynos5_gpio_part1 { struct s5p_gpio_bank a0; struct s5p_gpio_bank a1; @@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) +#define exynos4x12_gpio_part1_get_nr(bank, pin) \ + ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ + EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + +#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part2_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ + EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) + +#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ + / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) + +#define exynos4x12_gpio_part3_get_nr(bank, pin) \ + (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ + EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ + - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ + * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) + #define exynos5_gpio_part1_get_nr(bank, pin) \ ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ EXYNOS5_GPIO_PART1_BASE)->bank)) \