From patchwork Tue Oct 2 09:51:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 188438 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CF42F2C00A8 for ; Tue, 2 Oct 2012 19:52:18 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6A434280C6; Tue, 2 Oct 2012 11:52:17 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t7GqB0nGhOYH; Tue, 2 Oct 2012 11:52:17 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6A423280B6; Tue, 2 Oct 2012 11:52:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2F15D280B6 for ; Tue, 2 Oct 2012 11:52:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7dvnLVvv5O5G for ; Tue, 2 Oct 2012 11:52:13 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pb0-f44.google.com (mail-pb0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTPS id 0F01D280B4 for ; Tue, 2 Oct 2012 11:52:11 +0200 (CEST) Received: by pbbro8 with SMTP id ro8so8855025pbb.3 for ; Tue, 02 Oct 2012 02:52:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=FRYH8nZozA/NQr/5lz1ohlDJA+T3ak6rYqO2gBJ2fUg=; b=L6aLhGnhj28lXbxcgE709QpsDDvN8SsvsQFgktuJu6jBOMGRGo7n9EzZPAGJtc3s56 4JpLxWtIbzVXFzllx0VEnUlpLbb+1I7HUg4kVatcVD6xYNa4ramKX2KxytPWBqN88adq OybV3J/pKu0me1aeB3iMC3NQQ3F+cKIBJ2SKk9iHL2l9Ls+VggMZ8LaQw+6t7irdLsZq cf5/NeoeSLYCPN3oX+4CjISGwHZDOVMBRZxSo6+dqHTjADk3hWZtQKWOnXq+kBQSH6zh QabU7s2c5WS7i3zq2WVPWOUumaonzTbMOgy3kW2ZifuLEA4h13ZmV53YcGERDdcpmDzy E5LA== Received: by 10.68.213.199 with SMTP id nu7mr2939514pbc.75.1349171529835; Tue, 02 Oct 2012 02:52:09 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id bm8sm492409pab.3.2012.10.02.02.52.07 (version=SSLv3 cipher=OTHER); Tue, 02 Oct 2012 02:52:09 -0700 (PDT) From: Chander Kashyap To: u-boot@lists.denx.de Date: Tue, 2 Oct 2012 15:21:57 +0530 Message-Id: <1349171517-13931-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQnSuveNTqwspCdxBHt2R+0vHNeLMtKovoB5aUf277Ho3Y+qX29GEsUbQElwZPAk/7c+myoj Cc: linaro-dev@lists.linaro.org, patches@linaro.org Subject: [U-Boot] [PATCH] EXYNOS: Clock: Add common function for pll rate calculation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Moved the common code to calculate pll clock rate to new funtion exynos_get_pll_clk(). Signed-off-by: Chander Kashyap --- arch/arm/cpu/armv7/exynos/clock.c | 102 ++++++++++++++----------------------- 1 file changed, 38 insertions(+), 64 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4f3b451..a042423 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,41 +26,19 @@ #include #include -/* exynos4: return pll clock frequency */ -static unsigned long exynos4_get_pll_clk(int pllreg) +/* exynos: return pll clock frequency */ +static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) { - struct exynos4_clock *clk = - (struct exynos4_clock *)samsung_get_base_clock(); - unsigned long r, m, p, s, k = 0, mask, fout; + unsigned long m, p, s = 0, mask, fout; unsigned int freq; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - /* * APLL_CON: MIDV [25:16] * MPLL_CON: MIDV [25:16] * EPLL_CON: MIDV [24:16] * VPLL_CON: MIDV [24:16] + * BPLL_CON: MIDV [25:16]: Exynos5 */ - if (pllreg == APLL || pllreg == MPLL) + if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) mask = 0x3ff; else mask = 0x1ff; @@ -92,13 +70,43 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return fout; } +/* exynos4: return pll clock frequency */ +static unsigned long exynos4_get_pll_clk(int pllreg) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos5: return pll clock frequency */ static unsigned long exynos5_get_pll_clk(int pllreg) { struct exynos5_clock *clk = (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long r, m, p, s, k = 0, mask, fout; - unsigned int freq, pll_div2_sel, fout_sel; + unsigned long r, k = 0, fout; + unsigned int pll_div2_sel, fout_sel; switch (pllreg) { case APLL: @@ -123,41 +131,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return 0; } - /* - * APLL_CON: MIDV [25:16] - * MPLL_CON: MIDV [25:16] - * EPLL_CON: MIDV [24:16] - * VPLL_CON: MIDV [24:16] - * BPLL_CON: MIDV [25:16] - */ - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL) - mask = 0x3ff; - else - mask = 0x1ff; - - m = (r >> 16) & mask; - - /* PDIV [13:8] */ - p = (r >> 8) & 0x3f; - /* SDIV [2:0] */ - s = r & 0x7; - - freq = CONFIG_SYS_CLK_FREQ; - - if (pllreg == EPLL) { - k = k & 0xffff; - /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 65536) * (freq / (p * (1 << s))); - } else if (pllreg == VPLL) { - k = k & 0xfff; - /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */ - fout = (m + k / 1024) * (freq / (p * (1 << s))); - } else { - if (s < 1) - s = 1; - /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */ - fout = m * (freq / (p * (1 << (s - 1)))); - } + fout = exynos_get_pll_clk(pllreg, r, k); /* According to the user manual, in EVT1 MPLL and BPLL always gives * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/