@@ -24,6 +24,10 @@
#ifndef __ASM_ARCH_MX31_IMX_REGS_H
#define __ASM_ARCH_MX31_IMX_REGS_H
+#define CSPI1_BASE_ADDR 0x43fa4000
+#define CSPI2_BASE_ADDR 0x50010000
+#define CSPI3_BASE_ADDR 0x53f84000
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
@@ -99,6 +99,10 @@
#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
@@ -71,6 +71,9 @@
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_7 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
#define CONFIG_MXC_GPIO
/*
@@ -69,6 +69,11 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
+#define CONFIG_SPI_VER_0_5 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
+
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
@@ -213,6 +213,10 @@
#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
#define CONFIG_CMD_SPI
#define CONFIG_S6E63D6
@@ -65,6 +65,10 @@
#define CONFIG_HARD_SPI 1
#define CONFIG_MXC_SPI 1
+#define CONFIG_SPI_VER_0_5 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_MXC_GPIO
@@ -67,6 +67,10 @@
#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
@@ -62,9 +62,15 @@
#define CONFIG_SYS_I2C_MX35_PORT1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0xfe
-#define CONFIG_MXC_SPI
#define CONFIG_MXC_GPIO
+/*
+ * SPI Configs
+ */
+#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_7 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
/*
* PMIC Configs
@@ -68,6 +68,10 @@
#define CONFIG_CMD_SPI
#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_2_3 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
/* PMIC Controller */
#define CONFIG_PMIC
@@ -56,6 +56,10 @@
#define CONFIG_HW_WATCHDOG
#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13XXX
@@ -151,6 +151,11 @@
#define CONFIG_SYS_MX31_UART2
#define CONFIG_MXC_SPI
+#define CONFIG_SPI_VER_0_5 1
+#define CONFIG_CSPI1_BASE_ADDR CSPI1_BASE_ADDR
+#define CONFIG_CSPI2_BASE_ADDR CSPI2_BASE_ADDR
+#define CONFIG_CSPI3_BASE_ADDR CSPI3_BASE_ADDR
+
#define CONFIG_MXC_GPIO
/* MC13783 connected to CSPI3 and SS0 */
Apply new mxc_spi version configs to other soc configs. Signed-off-by: Terry Lv <r65388@freescale.com> --- arch/arm/include/asm/arch-mx31/imx-regs.h | 4 ++++ include/configs/efikamx.h | 4 ++++ include/configs/flea3.h | 3 +++ include/configs/imx31_litekit.h | 5 +++++ include/configs/imx31_phycore.h | 4 ++++ include/configs/mx31ads.h | 4 ++++ include/configs/mx31pdk.h | 4 ++++ include/configs/mx35pdk.h | 8 +++++++- include/configs/mx51evk.h | 4 ++++ include/configs/qong.h | 4 ++++ include/configs/tt01.h | 5 +++++ 11 files changed, 48 insertions(+), 1 deletions(-)